Introduction: Field Programmable Gate Array #FPGA System on Chip #SoC #Nios_II_Processor Hard Processor System #HPS Advanced RISC Machine #ARM Logical bridges Share physical resources Related Works: Renovell et Al., testing #RAM modules in #FPGA Focus on functional tests RAM of the FPGA Wei et Al., RAM memory monitoring Embedded System from the #HardProcessor Wang et Al., Real-time applications Use memory optimized way during the execution of tasks based on SoC architecture real-time Electrocardiogram #ECG FPGA with two 8GB Dual Data Rate Synchronous Dynamic Random Access Memories #DDR3 #SDRAM Results: As shown in Fig 12, the SRAM is working in the logical part executing several tasks and it is validated that as time passes the memory consumption increases. In addition, the writing times will depend on the amount of memory to be written and this varies according to the task that is being executed by the user or those that he has programmed in the Nios II. As for the DD3, it is executing the Linux OS as a basis and additionally, a size proportional to the size of the SRAM is reserved for the respective comparisons, so it is observed that it has a higher consumption and longer response times. It should be considered in this comparison that the DD3 in addition to running the OS, also has the web server implemented which consumption varies according to the clients that are connecting to the webpage where it can be seen the memory monitoring of the embedded system. Also, thanks to the part of the HPS it is possible to monitor the memory of the embedded system without affecting its consumption. As shown in Fig. 13, the SRAM is not under the same workload since it is only responsible for storing what Nios II needs for the execution of the tasks. Finally, it was consider that the HPS portion to be very important for a clean monitoring not only of the SRAM but also of any core that is implemented in the FPGA portion, since if this application is implemented on a chip that only has FPGA the application would affect the consumption and performance of it, therefore you could not have completely reliable results.

1. Monitoring of system memory usage
embedded in FPGA
Víctor Asanza , Nathaly Sánchez, Rommel Saquicela and Luis Macas
Escuela Superior Politécnica del Litoral, ESPOL, Guayaquil, Ecuador
Facultad de Ingeniería en Electricidad y Computación, FIEC

2. Topics
• Introduction
• Related Works
• Methodology
• Results
• Discussion and Conclusions
• More FPGA projects
Monitoring of system memory usage
embedded in FPGA

3. • Field Programmable Gate Array (FPGA)
• System on Chip (SoC)
• Nios II Processor
• Hard Processor System (HPS)
• Advanced RISC Machine (ARM)
• Logical bridges
• Share physical resources
Introduction
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html
Field Programmable Gate Arrays (FPGAs)

4. Field Programmable Gate Arrays (FPGAs)
Introduction
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html

5. Introduction
Hardware Design (Hard-processor ARM)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html

6. Introduction
Hardware Design (Hard-processor ARM)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html

7. Introduction
Hardware Design (Hard-processor ARM)
For more information about Hardware Design, check the link:
ELECTRONIC PROTOTYPES DESIGN
https://vasanza.blogspot.com/p/shared-material.html

8. Field Programmable Gate Arrays (FPGAs)
Introduction
Configurable Design (MSI)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html

9. Introduction
Configurable Design (Soft-processor NIOS II)
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html

10. Introduction
Hard-processor vs Software-processor
Arreglos de puertas lógicas programable
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html

11. DE10NANO - Terasic
Arquitectura H/S Processor - Cyclone V
NIOS II
processor
Introduction
Field Programmable Gate Arrays (FPGAs)
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html

12. Field Programmable Gate Arrays (FPGAs)
Introduction
Multiprocessor architectures

13. Field Programmable Gate Arrays (FPGAs)
Introduction
Ejemplo: Runtime CPU ARM Architecture
515 ms

14. Field Programmable Gate Arrays (FPGAs)
Introduction
Ejemplo: Runtime NIOSIIx2 Multiprocessor System
* Es 2,076 veces más rápido
248 ms

15. • Renovell et Al., testing RAM modules in FPGA
• Focus on functional tests RAM of the FPGA
• Wei et Al., RAM memory monitoring
• Embedded System from the Hard Processor
• Wang et Al., Real-time applications
• Use memory optimized way during the
execution of tasks based on SoC architecture
• real-time Electrocardiogram (ECG)
• FPGA with two 8GB Dual Data Rate
Synchronous Dynamic Random Access
Memories (DDR3 SDRAM)
Related Works
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.

16. Representation of communication between FPGA and HPS
Methodology
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.

17. Flow chart of the Nios II process
Methodology
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.
Process flow chart in Linux (HPS)

18. Resources used of FPGA
Results
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.

19. Average SRAM usage when executing tasks
Task Execution Time in SRAM
Results
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.

20. Task usage percentage in DDR3Average Execution Time in DDR3
Results
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.

21. Comparison in Usage of memory vs. Time Comparison of memory usage
Discussion and Conclusions
V. A. Armijos, N. S. Chan, R. Saquicela and L. M. Lopez, "Monitoring of system memory
usage embedded in FPGA," 2020 International Conference on Applied Electronics (AE),
Pilsen, Czech Republic, 2020, pp. 1-4, doi: 10.23919/AE49394.2020.9232863.

22. More FPGA projects
For more information about FPGA, check the link:
DIGITAL SYSTEMS 1, DIGITAL SYSTEMS 2, DIGITAL SYSTEMS DESIGN and VHDL
https://vasanza.blogspot.com/p/shared-material.html

23. More FPGA projects
Asanza V., Sanchez G., Cajo R., Peláez E. (2021) Behavioral Signal Processing with Machine
Learning Based on FPGA. In: Botto-Tobar M., Zamora W., Larrea Plúa J., Bazurto Roldan J.,
Santamaría Philco A. (eds) Systems and Information Sciences. ICCIS 2020. Advances in Intelligent
Systems and Computing, vol 1273. Springer, Cham. https://doi.org/10.1007/978-3-030-59194-6_17
Behavioral Signal Processing with Machine Learning Based on FPGA

24. More FPGA projects
Behavioral Signal Processing with Machine Learning Based on FPGA
Overview of our proposed architecture
Results obtained while testing different ser of neurons in
Hidden Layer
Resources used by FPGA
Asanza V., Sanchez G., Cajo R., Peláez E. (2021) Behavioral Signal Processing with Machine
Learning Based on FPGA. In: Botto-Tobar M., Zamora W., Larrea Plúa J., Bazurto Roldan J.,
Santamaría Philco A. (eds) Systems and Information Sciences. ICCIS 2020. Advances in Intelligent
Systems and Computing, vol 1273. Springer, Cham. https://doi.org/10.1007/978-3-030-59194-6_17

25. More FPGA projects
V. Asanza, A. Constantine, S. Valarezo and E. Peláez, "Implementation of a Classification
System of EEG Signals Based on FPGA," 2020 Seventh International Conference on
eDemocracy & eGovernment (ICEDEG), Buenos Aires, Argentina, 2020, pp. 87-92, doi:
10.1109/ICEDEG48599.2020.9096752.
Implementation of a Classification System of EEG Signals Based on FPGA
64 surface EEG Electrodes International System
(10/10)
Asanza, V., Pelaez, E., & Loayza, F. (2017, October).
Supervised pattern recognition techniques for detecting motor
intention of lower limbs in subjects with cerebral palsy.
In Ecuador Technical Chapters Meeting (ETCM), 2017
IEEE (pp. 1-5). IEEE.

26. More FPGA projects
V. Asanza, A. Constantine, S. Valarezo and E. Peláez, "Implementation of a Classification
System of EEG Signals Based on FPGA," 2020 Seventh International Conference on
eDemocracy & eGovernment (ICEDEG), Buenos Aires, Argentina, 2020, pp. 87-92, doi:
10.1109/ICEDEG48599.2020.9096752.
Implementation of a Classification System of EEG Signals Based on FPGA
Block diagram of data processing in FPGA
NIOS II processor
Diagram of the pattern recognition function of neural
networks in Simulink Multi-Layer Perceptron (MLP)
EEG Signals
Data Set
Signals
Preprocessing
7-30 Hz
Features Extraction Classification

27. More FPGA projects
V. Asanza, A. Constantine, S. Valarezo and E. Peláez, "Implementation of a Classification
System of EEG Signals Based on FPGA," 2020 Seventh International Conference on
eDemocracy & eGovernment (ICEDEG), Buenos Aires, Argentina, 2020, pp. 87-92, doi:
10.1109/ICEDEG48599.2020.9096752.
Implementation of a Classification System of EEG Signals Based on FPGA
Confusion Matrix of the classification
of all events
Logic utilization (Cyclone V)
1,303 / 41,910
(4%)
Total block memory bits
47,360 /5,662,720
(<1%)
Total pins
45/499
(9%)
Resources used by the fpga
crossval(trainedClassifier.Classification, 'KFold', 5);
• ME2 events with 92,1% accuracy
• IE2 events with 93,8% accuracy
Time to look for the file in the SD 21,26 [us]
Time to open the file in the SD 22,30 [us]
Processing time of the neural
network
27,36 [us]

28. More FPGA projects
C. Cedeño Z., J. Cordova-Garcia, V. Asanza A., R. Ponguillo and L. Muñoz M., "k-NN-Based EMG Recognition for
Gestures Communication with Limited Hardware Resources," 2019 IEEE SmartWorld, Ubiquitous Intelligence &
Computing, Advanced & Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing,
Internet of People and Smart City Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI), Leicester, United
Kingdom, 2019, pp. 812-817.
k-NN-Based EMG Recognition for Gestures Communication with Limited Hardware Resources

29. More FPGA projects
Artificial Neural Network based EMG recognition for gesture communication
Innovate FPGA 2019: Artificial Intelligence at the Edge!
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS027

30. More FPGA projects
Innovate FPGA 2019: Artificial Intelligence at the Edge!
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS027
Artificial Neural Network based EMG recognition for gesture communication

31. More FPGA projects
EMG Signal Processing with Clustering Algorithms for motor gesture Tasks
Asanza, V., Peláez, E., Loayza, F., Mesa, I., Díaz, J., & Valarezo, E. (2018, October). EMG
Signal Processing with Clustering Algorithms for motor gesture Tasks. In 2018 IEEE Third
Ecuador Technical Chapters Meeting (ETCM) (pp. 1-6). IEEE
https://www.myo.com/

32. State of the art
A survey of FPGA-based accelerators for convolutional neural networks
Mittal, S. (2020). A survey of FPGA-based accelerators for convolutional
neural networks. Neural computing and applications, 1-31.

33. State of the art
A survey of FPGA-based accelerators for convolutional neural networks
Mittal, S. (2020). A survey of FPGA-based accelerators for convolutional
neural networks. Neural computing and applications, 1-31.

34. Víctor Asanza
Mail: vasanza@espol.edu.ec
Facultad de Ingeniería en Electricidad y Computación, FIEC
Escuela Superior Politécnica del Litoral, ESPOL
Campus Gustavo Galindo Km 30.5 Vía Perimetral, P.O. Box 09-01-5863
090150 Guayaquil, Ecuador
Published in: https://ieeexplore.ieee.org/abstract/document/9232863
For more information

35. Thank you!