Programmable Logic Devices : SPLD and CPLD
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Programmable Logic Devices : SPLD and CPLD
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Programmable Logic Devices : SPLD and CPLD
- 1. Simple Programmable Logic Devices & Complex Programmable Logic Devices Dr Usha Mehta, Professor (EC) usha.mehta@nirmauni.ac.in
- 2. Programmable Logic Devices • What is the meaning of Programmable? • As its name consist of word “programmable”, is it similar to programming like in C and C++ ??? 12/8/2023 Usha Mehta 2
- 3. What does PLD means? • Programmable: ▪ Non programmable ▪ One Time Programmable ▪ Mask Programmable ▪ Fuse Programmable ▪ Reprogrammable ▪ Factory Programmable ▪ In-Situ Programmable ▪ Field Programmable ▪ Reconfigurable • Logic: • Devices: ▪ Design Vs Device 12/8/2023 Usha Mehta 3
- 4. Programmable….. ▪Non programmable ▪One Time Programmable ▪Mask Programmable ▪Fuse Programmable ▪Reprogrammable ▪Factory Programmable ▪In-Situ Programmable ▪Field Programmable ▪Reconfigurable 12/8/2023 Usha Mehta 4
- 5. Why PLDs? • Compared to discrete devices in board? • Compared to ASICs? • Pl. consider…. ▪ Instant turn around ▪ Low start up cost ▪ Low financial risk ▪ Ease of design changes ▪ Complexity ▪ Security………. 12/8/2023 Usha Mehta 5
- 6. Types of PLD PLD Simple PLD PROM PLA PAL High Capacity PLD CPLD FPGA 12/8/2023 Usha Mehta 6
- 7. SPLD ▪ PLAs, PALs, and ROMs are also called SPLDs – Simple Programmable Logic Devices ▪ SPLDs must be programmed so that the switches are in the correct places ✓CAD tools are usually used to do this • A fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit ✓There are two basic types of programming techniques • Removable sockets on a PCB • In system programming (ISP) on a PCB • This approach is not very common for PLAs and PALs but it is quite common for more complex PLDs 12/8/2023 Usha Mehta 7
- 8. Symbology A PLD can have hundreds to millions of gates interconnected through hundreds to thousands of internal paths . In order to show the internal logic diagram of such a device a special symbology is used 12/8/2023 Usha Mehta 8
- 11. Programmable Logic Devices And/Or Plane Examples 12/8/2023 Usha Mehta 11
- 12. PROM Architecture • Generate sum of products • Each output line is sum of minterms of the k inputs • This example has 8 functions of 5 inputs 12/8/2023 Usha Mehta 12
- 13. Design a circuit which generates square of 3-bit number. • Input:3 • Output:6 • Truth table • Try to reduce PROM requirement 12/8/2023 Usha Mehta 13
- 14. Design a converter to convert binary number ranging 0 to 99 into BCD • Inputs: ▪ Binary number 0 to 99 ▪ total 7 binary bits to represent 99 ▪ Inputs I0 to I6 • Outputs ▪ Two BCD numbers to represent the 00 to 99 ▪ Outputs F0 to F7 • Decoder and PROM Size ▪ 7 inputs i.e. 7 to 128 decoder ▪ 8 outputs i.e. 128 X 8 PROM • Prepare the truth table ▪ 0 to 99 : output equals two digit BCD number ▪ 100 to 127 : all one’s indicating invalid inputs 12/8/2023 Usha Mehta 14
- 15. • Implement F = ∑(10, 11, 14, 15) using PROM. 12/8/2023 Usha Mehta 15
- 16. Implementation of FSM with PROM • For state machine, map state table directly into memory ▪ Address lines driven by present state and present input ▪ Data outputs consist of next state and present output ▪ Both Mealy and Moore machines can be realized • Output of Moore machine lags by one clock period (when state table directly mapped) 12/8/2023 Usha Mehta 16
- 17. “101” Sequence Detector • Mealy Machine 12/8/2023 Usha Mehta 17
- 20. PLA Implementation • Try to reduce the number of product terms -To use fewer of the rows • Number of literals in each term not as important - Fewer may make circuit faster Like programmable inverter Tied to 0 – F1 not inverted Tied to 1 – F1 is inverted 12/8/2023 Usha Mehta 20
- 21. Implementation using PLA = ) 4 , 2 , 1 , 0 ( ) , , ( 1 m C B A F = ) 7 , 6 , 5 , 0 ( ) , , ( 2 m C B A F BC AC AB F + + = 1 C B A AC AB F + + = 2 12/8/2023 Usha Mehta 21
- 23. No Product Term Sharing Fixed from Factory 12/8/2023 Usha Mehta 23
- 24. PAL with Function Sharing or Additional Inputs 12/8/2023 Usha Mehta 24
- 25. PAL Architecture contd.. • OR circuit not as versatile • This PAL 4 in, 4 out • But only 3 ANDs • Note : – F1 fed back as one product term – Possible to expand 12/8/2023 Usha Mehta 25
- 26. Implementation using PLA = ) 4 , 2 , 1 , 0 ( ) , , ( 1 m C B A F = ) 7 , 6 , 5 , 0 ( ) , , ( 2 m C B A F BC AC AB F + + = 1 C B A AC AB F + + = 2 12/8/2023 Usha Mehta 26
- 27. PAL Architecture Programmable AND plane. Fixed OR plane. 12/8/2023 Usha Mehta 27
- 28. = ) 13 , 12 , 2 ( ) , , , ( m D C B A W = ) 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 , 7 ( ) , , , ( m D C B A X = ) 15 , 11 , 10 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 0 ( ) , , , ( m D C B A Y = ) 13 , 12 , 8 , 2 , 1 ( ) , , , ( m D C B A Z D C B A C AB W + = D C B A D C A D C B A C AB Z + + + = D C B A D C A W Z + + = Implementation using PAL 12/8/2023 Usha Mehta 28
- 30. PALxxyzz Nomenclature • XX maximum number of AND Array inputs • ZZ maximum number of dedicated outputs • Y Type of Output ▪ H: Active High ▪ L: Active Low ▪ P: Programmable ▪ C: Complimentary ▪ R: Registered ▪ RP: Registered with Programmable Polarity ▪ V: Versatile Programmable as combinational or registered 12/8/2023 Usha Mehta 30
- 31. • PAL3H2 ▪ 3 inputs ▪ 2 outputs ▪ Active High outputs • PAL16L8 ▪ 16 inputs ▪ 8 outputs ▪ Active Low outputs ( Function of 0s) • PAL22V10 12/8/2023 Usha Mehta 31
- 32. 16R4 PAL: 16 i/p variable, 4 registered outputs 12/8/2023 Usha Mehta 32
- 34. Segment of Sequential PAL 12/8/2023 Usha Mehta 34
- 35. SPLD 22CEV10 • CMOS EEPLD • 12 dedicated i/ps, 10 I/Os, 10 Dffs, 10 OR gates • 22 Inputs CMOS Electrical erasable Versatile 10 Registered Ouutputs • It means 10 Flipflops, 10 Macrocells 12/8/2023 Usha Mehta 35
- 39. CPLD
- 40. Complex PLD Architecture Ref. Xilinx White paper on 9500 CPLD 12/8/2023 Usha Mehta 40
- 43. Macrocell Clock and Set/Reset Capabilities 12/8/2023 Usha Mehta 43
- 45. Product Term Allocator Logic 12/8/2023 Usha Mehta 45
- 46. Fast Connect Switch Matrix 12/8/2023 Usha Mehta 46
- 47. I/O Blocks and Output Enable Capability 12/8/2023 Usha Mehta 47
- 48. Other Features • Pin Locking Capability: ▪ locked the used defined pins even when architecture has been changed • Endurance: 10000 program/erase cycles • In system Programming 12/8/2023 Usha Mehta 48
- 49. Evolution from CPLD • Approach to building a “better” PLD is place a lot of primitive gates on a die, and then place programmable interconnect between them: 12/8/2023 Usha Mehta 49
- 50. Programming of CPLD ▪ PLAs, PALs, and ROMs are also called SPLDs – Simple Programmable Logic Devices ▪ SPLDs must be programmed so that the switches are in the correct places ✓CAD tools are usually used to do this • A fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit ✓There are two basic types of programming techniques • Removable sockets on a PCB • In system programming (ISP) on a PCB • This approach is not very common for PLAs and PALs but it is quite common for more complex PLDs
- 51. An SPLD Programming Unit – The SPLD is removed from the PCB, placed into the unit and programmed there
- 53. CAD Design Flow for SPLD 12/8/2023 Usha Mehta 53