Pentium microprocessor

1. UNIT 6:PENTIUM
PROPROCESSOR

2. INTRODUCTION TO PENTIUM
PROPROCESSOR :
 The Pentium Proprocessor Is a sixth generation x86 microprocessor
developed and manufactured by intel and introduced and
November and 11995.
 This the figure of pin out of the Pentium pro processor
 The Pentium pro is available in two versions : one version contain a
the 256k level cache; the order 512k level 2 catch.
 It has 36 bit address bus which to allows access to 64GB memory.
 It has error correction circuitry that can fix 1 –bit of error.
 The important change in this processor was use of dynamic
execution instead of superscalar architecture.

3. INTERNAL STRUCTURE OF PENTIUM PRO
PROCESSOR :
 Pentium pro has 8 KB instruction cache ,which up to 16 Bytes are Fetched on each cycle and sent
to the instruction decoders
 The Pentium pro processor consist of
1] 8 K byte code cache
2] 8k byte data cache
3] Translation look aside buffer (TLB)
4] Branch trace buffer (BTB)
5] Integer pipelines U and V
6] Floating –point pipeline
7] Microcode ROM and control unit (CU)
* The BTB is used to store the target address and statistical info about the branch operation .
* Control unit controls the five stage integer pipelines U and V and eight Floating –Point in
architecture of Pentium proprocessor .

5. The Memory System :
 The memory system for Pentium microprocessor is 4G bytes in size just as in
80386 DX & 80486 microprocessor.
 Pentium uses a 64-bit data bus to address memory organized in eight banks
that each contains 512 M bytes of data.
 The Pentium pro thus featured out of order execution, including speculative
execution via register remaining .It also had a wider 34-bit address bus
usable by physical Address Extension (PAE).

6. Special Pentium pro Features :
 The Pentium pro is essentially the same microprocessor as the 80386,80486
and Pentium , except that some additional features and changes to the
control register set have occurred.
 1] 32-bit address bus
 2] 64 –bit data bus
 Built –in floting –point
 Memory –management units
 Two eight –kilobyte caches.

7. Hyperthreading technology :
 It is a most recent innovation .
 It contains combination of two microprocessors into a single
package.
 The hyper – threaded processor contains two execution units that
each contain a complete set of the registers , capable of running
software independently or concurrenty.
 These two separate machine context share a common bus interface
unit .
 The bus interface unit is in use to use to access memory it is often
idle.
 Because of this second processor can use this idle time to access
memory .
 In most cases the system performance increases with hyper –
threading achieving nearly the same performance as with a dual
processor system

8. MULTIPLE CORE TECHNOLOGY
 Most new versions of Pentium 4 and core 2 contain either dual or quad
cores.
 Each core is a separate version of the mp that independently executes a
separate task.
 The versions are Pentium D , Core 2 Duo
 Core 2 Duo contains either 2M or 4M byte cache at frequencies to 3GHZ.

9. CPUID
 As in earlier versions of the Pentium , the
CPUID instruction accesses info.features
supported by the MP
 Table 19-7 lists the latest features available
to the CPUID .
 To access these features , EAX is loaded with
the input no.listed in the table , then the
CPUID instruction is executed.