Inverters_VLSI_Design powerpoint presentation

5 March 2024 VLSI Design 1
5 March 2024 1
5 March 2024 1
VLSI Design
Dr. T R Lenka
Asst. Professor
Deptt of Electronics & Comm Engg.
National Institute of Technology Silchar
E-mail: trlenka@ece.nits.ac.in
MOS Inverters

Assignment-1
1. Explain the operation principle of MOSFET using
energy band diagrams in accumulation,
depletion & inversion regions.
2. Derive the expression of threshold voltage and
flat band voltage.
3. Derive the expression of drain currents in all
regions of operation (Cut-off, Linear &
Saturation).
4. Find the expression of transconductance.
5. Draw the C~V characteristics of MOSFET.

5 March 2024 3
Chapter Coverage
Static Characteristics
Dynamic Characteristics

Inverter

Ideal Voltage Transfer
Characteristic (VTC)

General Circuit Structure of
an nMOS Inverter

Voltage Transfer
Characteristic (VTC)

VTC
• Applying Kirchhoff’s Current Law
(KCL), the Load current is always
equal to the nMOS drain current.
ID (Vin, Vout)=IL(VL)
• Two critical voltage points (VIL,VIH)
defined on this VTC curve, where the
slope of the Vout (Vin) characteristic
becomes equal to -1.

Critical Voltages
• VOH:Maximum output voltage when the
output level is logic “1”.
• VOL:Minimum output voltage when the
output level is logic “0”.
• VIL:Maximum input voltage which can be
interpreted as logic “0”.
• VIH:Minimum input voltage which can be
interpreted as logic “1”.
• VTH:Threshold voltage of inverter, is
defined as the point, where Vin=Vout.

Noise Immunity and Noise
Margins
• The ability of an inverter to interpret
an input signal within a voltage
range as either a logic “0” or as a
logic “1”, allows digitals circuits to
operate with a certain tolerance to
external signal perturbations.

Cascaded Inverters

Noise Immunity and Noise
Margins

Noise Margins

Noise Margins
• Noise tolerances for digital circuits,
called, Noise Margin (NM).
• NML=VIL-VOL :Noise Margin Low
• NMH=VOH-VIH :Noise Margin High
• The noise immunity of the circuit
increases with NM

Resistive Load Inverter

• Calculation of VOH:
Vout= VDD–RL.IR , where (ID=IR)
• When Vin is low, i.e., smaller than the
threshold voltage of the driver MOSFET,
the driver transistor is cut-off.
• So ID=IR =0
• VOH =VDD

• Calculation of VOL:
• IR= IDLinear
• (VDD-VOUT)/RL= Kn/2[2(VDD-VTO).VOL- VOL
2]

• Calculation of VIL:
• IR= IDSaturation
• (VDD-VOUT)/RL= Kn/2[(Vin-VTO)2]

• Calculation of VIH:
• IR= IDLinear
• (VDD-Vout)/RL= Kn/2[(Vin-VTO).Vout-Vout
2]
• Differenting both sides w.r.t Vin and
substituting the slope=-1

Layout of Resistive Load
Inverter

Enhancement-nMOS Load
Inverter

Depletion-nMOS Load
Inverter

Depletion-nMOS Load Inverter
Calculation of VOH:
the driver transistor is cut-off and does
not conduct any drain current.
• ID, Driver, Cutoff=ID, Load, Lin=0 A
• The Load device which operates in the
linear region also has zero drain current.
• So ID, Load=0 A
• Only valid solution in the linear region is
VOH =VDD

Calculation of VOL:
• ID, Driver, Lin = ID, Load, Sat
• ID, Driver, Lin =(Kdriver/2)[2(VOH-VTO).VOL- VOL
2]
• ID, Load, Sat =(KLoad/2)[-VT, Load (VOL)]2

Calculation of VIL:
• ID, Driver, Sat = ID, Load, Lin
• ID, Driver, Sat =(KDriver/2)[Vin-VTO]2
• ID, Load, Sat =(KLoad/2){2[VT, Load (Vout)](VDD-
Vout)- (VDD-Vout)2}

Calculation of VIH:
• ID, Driver, Lin = ID, Load, Sat
• ID, Driver, Lin =(KDriver/2)[2(Vin-VTO) Vout-
Vout
2]
• ID, Load, Sat =(KLoad/2)[-VT, Load (Vout)]2

VTC of a Depletion-Load
Inverter Circuit

VTC of Depletion-Load
Inverter Circuits

Layout of Depletion-Load
Inverters

CMOS Inverter

VTC of CMOS Inverter

Region of Operation
Region Vin Vout nMOS pMOS
A <VT0,n VOH Cut-Off Linear
B VIL high≈VO
H
Saturation Linear
C Vth Vth Saturation Saturation
D VIH Low≈VOL Linear Saturation
E >(VDD+VT0,p) VOL Linear Cut-Off

CMOS Inverter
Calculation of VOH:
the driver transistor is cut-off and does
not conduct any drain current.
• ID, Driver, Cutoff=ID, Load, Lin=0 A
• The Load device which operates in the
linear region also has zero drain current.
• So ID, Load=0 A
• Only valid solution in the linear region is
VOH =VDD

CMOS Inverter
Calculation of VOL:
• ID, Driver, Lin = ID, Load, Cut-off
• ID, Driver, Lin =(Kdriver/2)[2(VDD-VTO).VOL- VOL
2]
• ID, Load, Cut-off =0A
• VOL =0 V

CMOS Inverter
Calculation of VIL:
• ID, nMOS, Sat = ID, pMOS, Lin
• ID, nMOS, Sat=(Kn/2)[VGS,n-VTO,n]2
• ID, pMOS, Lin=(KP/2)[2(VGS,p-VTO,p)VDS,p-VDS,p)2]
• VIL=(2Vout + VTO,p- VDD+ KRVTO,n)/(1+KR)
• Transconductance Ratio(KR)
• KR = Kn/KP

CMOS Inverter
Calculation of VIH:
• ID, Driver, Lin= ID, Load, Sat
• ID, nMOS, Lin= (Kn/2)[2(VGS,n-VTO,n)VDS,n-VDS,n)2]
• ID, pMOS, Sat=(Kp/2)[VGS,p-VTO,p]2
• VIH=(VDD+VTO,p+KR (2Vout+VTO,n))/(1+KR)
• KR = Kn/KP

CMOS Inverter
Calculation of Vth:
• ID, Driver, Sat= ID, Load, Sat
• ID, nMOS, Sat= (Kn/2)[2(VGS,n-VTO,n)2]
• ID, pMOS, Sat=(Kp/2)[VGS,p-VTO,p]2
• Vth=VTO,n+KR
-1/2(VDD+VTO,p)/(1+KR
-1/2)
• KR=Kn/KP

Design of CMOS Inverter

• CMOS inverter doesn’t draw any
significant current from power supply,
except for small leakage and sub-
threshold currents.
• These currents exist when input voltage is
either smaller than VTO,n or larger than
(VDD+VTO,p) repectively.
• The nMOS and pMOS transistors conduct a
non-zero current, during low-to-high and
high-to-low transitions, i.e. in Regions B,
C, D.

• The current drawn from the power supply
during transition reaches its peak value
when Vin=Vth.
• In other words, the maximum current is
drawn when both transistors are operating
in saturation mode.
• VTC of a CMOS inverter and the power
supply current, as a function of the input
voltage, is shown.

VTC & Power Supply Current
of a CMOS Inverter

• The threshold voltage Vth is identified as
one of he most important parameter that
characterize the steady-state input-output
behavior of the CMOS inverter circuit.
• The CMOS inverter, provides a full output
voltage swing between 0 and VDD and
therefore the noise margins (NM) are
relatively wider.
• So, the problem of designing a CMOS
inverter can be reduced to setting the
inverter threshold (Vth) to a desired
voltage value.
Design of CMOS Inverters

• Switching threshold voltage of an
ideal inverter is, Vth, ideal= VDD/2.
• The Inverter threshold voltage Vth
shifts to lower values with increasing
KR ratio.
• For a symmetric CMOS inverter with
VT0,n =VT0,p and KR=1.
• VIL= 1/8(3VDD+2 VT0,n)
• VIH= 1/8(5VDD-2 VT0,n)

• For a symmetric CMOS inverter with
VIL+ VIH= VDD
• The noise margins NML and NMH for
this symmetric CMOS inverter are
now calculated as:
• NML=VIL-VOL=VIL
• NMH=VOH-VIH=VDD-VIH
• NML=NMH=VIL

Supply Voltage Scaling in
CMOS Inverters
VDD
min=VT0,n + VT0,p

VTC of CMOS Inverter at
Lower VDD
min

Layout of CMOS Inverter

Design of D-nMOS Load
Inverter

Layout Design

Design of E-nMOS Load
Inverter

Design

5 March 2024 55
VLSI Design
Switching Characteristics of
MOS Inverters

Parasitic Capacitances

Load Capacitance

Rise Time - Fall Time

Charge Up

CMOS Inverter

Layout Design

Ring Osci

Output Waveforms

Interconnect

Typical Graph

Multi Level Metallization

Current Density

Capacitances

Fringe Capacitance

Graph

Calculation of Interconnect
Delay
• RC Delay Models
– An interconnect line can be modeled as
a lumped RC network if the time of
flight across the interconnection line is
significantly shorter than the signal
rise/fall times.
– This is usually the case in most on-chip
interconnects.

RC Delay Models
• Assuming that the capacitance is
discharged initially, and assuming that the
input signal is a rising step pulse at time t
= 0, the output voltage waveform of this
simple RC circuit is found as
• The rising output voltage reaches the
50%-point at t = TPLH, thus, we have

RC Delay Models
• The propagation delay for the simple
lumped RC network is found as
• The accuracy of the simple lumped RC
model can be significantly improved by
dividing the total line resistance into two
equal parts (the T-model)

RC Delay Models
• The transient behavior of an interconnect
line can be more accurately represented
using the RC ladder network, as shown.
• Here, each RC-segment consists of a
series resistance (R/N), and a capacitance
(C/N) connected between the node and
the ground.

RC Delay Models
• It can be expected that the accuracy of
this model increases with increasing N,
where the transient behavior approaches
that of a distributed RC line for very large
values of N.

The Elmore Delay
• Consider a general RC tree network.
– There are no resistor loops in this circuit
– All of the capacitors in an RC tree are
connected between a node and the
ground.
– There is one input node in the circuit.
– There is an unique path resistive path
from the input node to any other node
in the circuit.

The Elmore Delay
• Assuming that the input signal is a step
pulse at time t = 0 and the Elmore delay
at node i of this RC tree is given by the
following expression.

The Elmore Delay
• the Elmore delay at node 7 can be
found as
• Similarly, the Elmore delay at node 5
can be calculated as

The Elmore Delay
• As a special case of the general RC tree
network, consider now the simple RC
ladder network as shown.
• Here, the entire network consists of one
single branch, and the Elmore delay from
the input to the output (node N) is found
as:

The Elmore Delay
• If we further assume an uniform RC ladder
network, consisting of identical elements
of (R/N) and (C/N) then the Elmore delay
from the input to the output node
becomes:
• For very large N (distributed RC line
behavior), this delay expression reduces
to:

The Elmore Delay
• Thus, the propagation delay of a
distributed RC line is considerably smaller
than that of a lumped RC network.
• If the length of the interconnection line is
sufficiently large and the rise/fall times of
the signal waveforms are comparable to
the time of flight across the line, then the
interconnect line must be modeled as a
transmission line.

Switching Power Dissipation of
CMOS Inverters
• As discussed the static power
dissipation of the CMOS inverter is
quite negligible.
• The dynamic power consumption of
the CMOS inverter is derived.

• During switching events the output
load capacitance is alternatively
charged up and charged down.
Dynamic Power Dissipation Analysis

• The output load capacitance Cload is
being charged up through the pMOS
transistor; therefore, the capacitor
current equals the instantaneous
drain current of the pMOS transistor.
• The average power dissipated by the
inverter over one period can be
found as:

• Typical input and output voltage waveforms
and the capacitor current waveform during
switching of the CMOS inverter.

• Since during switching, the nMOS
transistor and the pMOS transistor in a
CMOS inverter conduct current for one-
half period each.
• The average power dissipation of the
CMOS inverter can be calculated as the
power required to charge up and charge
down the output load capacitance.

• Evaluating the integrals, we obtain
• The average power dissipation of the
CMOS inverter is proportional to the
switching frequency “f”.

Summary
• Therefore, the low-power advantage of CMOS
circuits becomes less prominent in high-speed
operation, where the switching frequency is
high.
• Also note that the average power dissipation
is independent of all transistor characteristics
and transistor sizes.
• Consequently, the switching delay times have
no relevance to the amount of power
consumption during the switching events.
• switching power is solely dissipated for
charging and discharging the output
capacitance from VOL to VOH, and vice versa.

Summary
• The switching power expression derived
for the CMOS inverter also applies to all
general CMOS circuits.

Power-Delay Product
• The power-delay product (PDP) is a
fundamental parameter which is often
used for measuring the quality and the
performance of a CMOS process and gate
design.
• As a physical quantity, the power-delay
product can be interpreted as the
average energy required for a gate to
switch its output voltage from low to high
and from high to low.
• The amount of energy required to switch
the output.

Power-Delay Product
• From a design point-of-view, it is desirable
to minimize the power-delay product.
• Since the PDP is a function of the output
load capacitance and the power supply
voltage, the designer should try to keep
both Cload and VDD as small as possible
when designing a CMOS logic gate.
• where is the average switching power
dissipation at maximum operating
frequency and is the average
propagation delay.
p

*
avg
p

Power-Delay Product
• The factor of 2 accounts for two
transitions of the output, from low to high
and from high to low.

5 March 2024 97
5 March 2024 97
VLSI Design
Combinational Logic
Circuits

Combinational Logic Circuit

NOR Gate using Depletion
type Load

Critical Voltages
• Calculation of VOH
– The solution of this equation gives
VOH = VDD.
• Calculation of VOL
– Three cases must be considered

Critical Voltages
• In case (i), where the driver transistor A is
on, the ratio is
• In case (ii), where the driver transistor B
is on, the ratio is
• The output low voltage level VOL in both
cases is found as:

Critical Voltages
• if the (W/L) ratios of both drivers are
identical, i.e., (W/L)A = (W/L)B the output
low voltage (VOL) values calculated for
case (i) and case (ii) will be identical.
• In case (iii), where both driver transistors
are turned on, the saturated load current
is the sum of the two linear-mode driver
currents.

Critical Voltages
• Since the gate voltages of both driver transistors
are equal (VA = VB = VOH), we can devise an
equivalent driver-to-load ratio for the NOR
structure:
• The NOR gate with both of its inputs tied to a
logic-high voltage is replaced with an nMOS
depletion-load inverter circuit with the driver-to-
load ratio (KR) having output voltage level:

Generalized NOR Structure with
Multiple Inputs

Generalized NOR Structure
• The combined pull-down current can then be
expressed as
• Assuming that the input voltages of all driver
transistors are identical and VGSk = VGS for
k=1,2,...,n. Then the pull-down current
expression can be rewritten as

Generalized NOR Structure
• Thus, the multiple-input NOR gate can
also be reduced to an equivalent inverter
for static analysis. The (W/L) ratio of the
driver transistor here is

Transient Analysis of NOR Gate

Two-Input NAND Gate using
Depletion type Load

NAND Gate using Depletion Load

Two-Input NAND Gate
• Consider the NAND2 gate with both of its
inputs equal to VOH.
• The drain currents of all transistors in the
circuit are equal to each other.
• Neglecting the substrate-bias effect for
driver transistor A for simplicity, we get

Two-Input NAND Gate
• The drain-to-source voltages of both
driver transistors can be
• Let the two driver transistors be identical,
i.e., kdriverA = kdriverB = kdriver
• The output voltage VOL is equal to the sum
of the drain-to-source voltages of both
drivers.

Two-Input NAND Gate
• The following analysis gives a better and
more accurate view of the operation of
two series-connected driver transistors.
• Now consider the two identical
enhancement-type nMOS transistors with
their-gate terminals connected and VTA =
VTB = VT0.
• Since IDA = IDB, this current can also be
expressed as

Two-Input NAND Gate
• Using VGSA = VGSB - VDSB
• Now let VGS = VGSB and VDS = VDSA + VDSB.
The drain-current expression can then be
written as follows.
• Thus, two nMOS transistors connected in
series and with the same gate voltage
behave like one nMOS transistor with keq
= 0.5 kdriver.

Generalized NAND Structure with
Multiple Inputs
• n-series-connected driver transistors,
assuming that the threshold voltages of all
transistors are equal to VT0.
• Hence, the (W/L) ratio of the equivalent
driver transistor is

Two-Input NAND Gate
• If the series-connected transistors are
identical, i.e., (W/L)1 = (W/L)2 =.. .=
(W/L), the width-to-length ratio of the
equivalent transistor becomes

n-input NAND Gate using
Depletion Load

Transient Analysis of NAND Gate

Transient Analysis of NAND Gate
• Assume, for example, that the input VA is equal
to VOH and the other input VB is switching from
VOH to VOL. In this case, both the output voltage
Vout, and the internal node voltage Vx will rise,
resulting in
• In its reverse case

CMOS Network

A CMOS NOR Gate with Inverter
Equivalent
 
n
p
p
T
DD
n
p
n
T
th
k
k
V
V
k
k
V
NOR
V
4
1
4
)
2
(
,
,





Dynamic Characteristics of
NOR Gate

Layout Design of NOR Gate

 
n
p
p
T
DD
n
p
n
T
th
k
k
V
V
k
k
V
NAND
V
2
1
2
)
2
(
,
,




A CMOS NAND Gate with Inverter
Equivalent

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