Are CPUs VMs Like Any Others? v1.0
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A presentation summarising FPGAs, their history, their benefits, and showing how to program them. It provides some historical background on the development of computers, from the Difference Engine to the Intel 4004 to the AMD Ryzen Threadripper PRO 3995WX. It shows how the number of transistors increased dramatically but also how this increase led to more complexity and more bugs. It then introduces Field-programmable gate arrays (FPGA) as an alternative. It then presents how to program such FPGA using data-flow graphs. It discusses some tools (Yosys, NextPnR, and IceStorm) and illustrates them with a typical "Hello World" (i.e., blinking an LED) using Cygwin on Windows 10.
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Are CPUs VMs Like Any Others? v1.0
- 1. Yann-Gaël Guéhéneuc This work is licensed under a Creative Commons Attribution-NonCommercial- ShareAlike 3.0 Unported License Are CPUs VMs Like Any Others? How did I fall into this rabbit hole? Version 1.0 2020/10/09
- 2. 2/84 Outline A bit of history About FPGAs Programming – Basics – Simulation – Deployment – More… Conclusion
- 3. 3/84 A BIT OF HISTORY
- 4. 4/84 A Bit of History Of course, we start with a bit of history! https://en.wikiquote.org/wiki/George_Santayana “Those who cannot remember the past are condemned to repeat it.” George Santayana (1863 –1952)
- 5. 5/84 A Bit of History Of course, we start with a bit of history! https://en.wikiquote.org/wiki/George_Santayana “Those who cannot remember the past are condemned to repeat it.” George Santayana (1863 –1952) Or to overlook it…
- 6. 6/84 At The Beginning of Times ENIAC machine, 1945 https://en.wikipedia.org/wiki/Difference_engine https://en.wikipedia.org/wiki/ENIAC https://www.engineering.com/ElectronicsDesign/ElectronicsDesignArticles/ ArticleID/16337/Vacuum-Tubes-The-World-Before-Transistors.aspx Difference engine, 1822
- 7. 7/84 A Bit Later… https://www.computerhistory.org/revolution/digital-logic/12/273 https://en.wikipedia.org/wiki/Intel_4004 Intel 4004, 1971 First bipolar junction transistors, 1947
- 8. 8/84 More Recently https://techgage.com/news/amd-rumored-to-soon-launch-ryzen-pro-version-of-threadripper-3990x-dubbed-3995wx/ https://www.techpowerup.com/cpu-specs/ryzen-threadripper-pro-3995wx.c2314 https://en.wikipedia.org/wiki/Transistor_count AMD Ryzen Threadripper PRO 3995WX 14th of July, 2020 (3,800 million transistors)
- 9. 9/84 Rich People’s Problems More and more transistors More and more complexity
- 11. 11/84 Rich People’s Problems AMD Ryzen Threadripper PRO 3995WX – 14th of July, 2020 – 3,800 million transistors Cerebras Wafer-Scale Engine – 28th of August, 2019 – 1.2 trillion transistors
- 12. 12/84 Rich People’s Problems More and more transistors More and more bugs
- 13. 13/84 (In)Famous CPU Bugs Pentium FDIV bug – Incorrect floating-point divisions – Missing entries in the lookup table of the floating-point division circuitry – Equivalent to $743 million in 2019
- 14. 14/84 (In)Famous CPU Bugs Intel x86 CPUs IBM POWER CPUS Some ARM CPUs – A process can read all the memory – CVE-2017-5754 – Unclear costs?
- 15. 15/84 FPGAS
- 16. 16/84 Alternatives? What if we could (re)program CPUs as we program/update software? FPGAs as alternative to CPUs – Field-programmable gate arrays – Integrated circuit configured after manufacturing https://en.wikipedia.org/wiki/Field-programmable_gate_array
- 18. 18/84 Field-programmable Gate Arrays A gate: OR, AND… – Any logic function can be built from gates An array: a set of unconnected gates Field-programmable: configured by a customer after manufacturing
- 19. 19/84 Field-programmable Gate Arrays https://www.ni.com/en-ca/innovations/white-papers/08/fpga-fundamentals.html Programmable interconnects between configurable logic blocks (CLBs)
- 20. 20/84 Applications Soft microprocessors Microprocessor cores Soft cores Intel 4004 CPU MOS 6502 Motorola 68000 … https://opencores.org
- 21. 21/84 More Applications Specialised algorithms – Monte Carlo methods – Map-Reduce algorithms – Neural networks – Encryption Specialised domains – Sensors/Actuators – Space probes – Cameras – F1 steering wheels – Video en/decoding – Audio/Video filtering – Software defined networks
- 22. 22/84 Typical Application FPGAArcade Replay 1 – 1.6M gates Xilinx Spartan 3E FPGA – PS/2 x2, Joysticks x2 – RS232, DVI, audio, S- video, Composite – JTAG, USB, SD Card http://www.mfilos.com/2015/08/fpga-arcade-new-led-signals-on-core.html
- 23. 23/84 Typical Application https://build.fpgaarcade.com/releases/cores/R1/ Computers – Amiga – C64 – VIC20 – … Arcades – Crystal Castles – Donkey Kong – Mr. Do! – …
- 24. 24/84 Even More Applications https://www.sparkfun.com/products/14829 https://www.mouser.ca/new/terasic-technologies/terasic-de10-nano-kit/ TinyFPGA Bx Board DE10-Nano Board
- 26. 26/84 Schizophrenia FPGA – Software (cores) – Hardware (chips, boards) Hardware description language – Verilog – VHDL
- 27. 27/84 Development Dynamic rather than static Data flow graphs rather than class diagrams Data flow graphs like in compiler design
- 28. 28/84 Data Flow Graphs (Procedure) Silvia Regina Vergilio, José Carlos Maldonado, and Mario Jino ; Infeasible Paths in the Context of Data Flow Based Testing Criteria: Identification, Classification and Prediction ; Journal of the Brazilian Computer Society, Springer, 2006
- 29. 29/84 Data Flow Graphs (Interprocedural) Rohan Padhye and Uday P. Khedker ; Interprocedural Data Flow Analysis in Soot using Value Contexts; Proceedings of the 2nd ACM SIGPLAN International Workshop on State Of the Art in Java Program analysis, ACM Press, 2013
- 30. 30/84 Development Time(ing) is of the essence Functions are like processes that trigger updates at the clock signal https://www.designboom.com/art/alex-chinneck-ties-antique-clock-05-18-2018/
- 31. 31/84 Time(ing)? Quantum Field Theory
- 32. 32/84 Time(ing)? Quantum Field Theory Another time ;-)
- 33. 33/84 Time(ing)? Synchronisation Cannot be faster than the slowest transition – Transistors – Memory – … Quantum Field Theory Another time ;-)
- 34. 34/84 Development https://course.ece.cmu.edu/~ee760/760docs/blif.pdf http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf BLIF: logic-level hierarchical circuit (text) ASC: PADS layout ASCII design files (?) BIN: binary bitstream Yosys • Verilog to BLIF NextPnR • BLIF to ASC IceStorm • ASC to BIN
- 35. 35/84 Development Yosys – Compiles Verilog into Berkeley Logic Interchange Format (BLIF), aka synthesis NextPnR – Decides which CLBs should implement what logic blocks of the design – Decides which programmable switches to turn ON to connect CLBs https://www.eng.uwo.ca/people/wwang/ece616a/616_extra/notes_web/5_dphysicaldesign.pdf
- 36. 36/84 Development IceStorm – Converts ASC to a binary file that can be upload onto the FPGA – Generates a bitstream – iCE is actually a brand name of Lattice Semiconductor, which produce FPGAs – Several FPGAs support their format because it is open source https://en.wikipedia.org/wiki/ICE_%28FPGA%29#Open_source
- 38. 38/84 Hello World? “Hello World” is the typical first program written in any language https://www.softwaretestinghelp.com/java/hello-world-first-java-program/
- 39. 39/84 Hello World! Blinking a LED is the typical first “program” written for any FPGA
- 40. 40/84 Hello World! “FPGA design for Software Engineers” – Jeff DeWall – 2019/10/16 – www.walknsqualk.com/post/014-tiny-fpga-bx/
- 41. 41/84 Development Jae-yeob Kim, Eui-sub Kim, Jun-beom Yoo, Young Lee, and Jong-gyun Choi ; An Integrated Software Testing Framework for FPGA-based Controllers in Nuclear Power Plants ; Nuclear Engineering and Technology, Elsevier, 2016
- 42. 42/84 Requirements Switch on a LED after some period of time
- 43. 43/84 Design
- 44. 44/84 Design TinyFPGA Bx defines – CLK – LED – USBPU (and many more)
- 45. 45/84 Windows 10 – Because why not? Cygwin – Let’s be serious! Simulation
- 46. 46/84 00_blinky contains 5 files – CMakeLists.txt Build directives – conanfile.txt C/C++ dependencies – main.cpp Test/Simulation driver – pins.pcf Physical constraints file – top.v Verilog module Simulation
- 47. 47/84 CMake . – To generate the Makefile and other files Make – To compile and generate the executable bin/blinky.exe – To simulate and generate trace.vcd GTKWave – To visualise trace.vcd Simulation
- 50. 50/84 Install CMake – Build process manager – Which led to adding all sort of dependencies Install Conan – C/C++ package manager – Which would not compile on Cygwin… – Which was missing conanbuildinfo.cmake… Simulation
- 51. 51/84 Install Yosys – A framework for Verilog RTL synthesis – Which would not compile on Cygwin… Install Project IceStorm – Place and route tool – Which would not compile on Cygwin… Simulation
- 52. 52/84 Install NextPnR – Place and route tool – Which would not compile on Cygwin… Fixes for the compilation – -DCMAKE_CXX_FLAGS=-std=c++11 – Implement strdup()... – Modify • /usr/local/share/verilator/include/verilated.cpp • /usr/local/share/verilator/include/verilatedos.h Simulation
- 55. 55/84 Simulation https://www.kindpng.com/imgv/ixoxiTx_alice-in-wonderland-and-the-white-rabbit-png/
- 56. 56/84 Simulation All the steps to simulate Simulate? – Value Change Dump (.vcd) – Timestamps – Values for each signal/variable
- 57. 57/84 Simulation
- 58. 58/84 Simulation
- 59. 59/84 Simulation
- 60. 60/84 Simulation The LED signal is up
- 62. 62/84 “FPGA design for Software Engineers” – Jeff DeWall – 2019/10/16 – www.walknsqualk.com/post/014-tiny-fpga-bx/ “TinyFPGA BX User Guide” – 2020/10/01 – https://tinyfpga.com/bx/guide.html Deployment ∧ ∧ ∧ ∧
- 63. 63/84 Windows 10 – Because why not? – Because it works! Cygwin – Not possible! Deployment
- 64. 64/84 Doesn’t work in Cygwin – Packages not (yet?) available Break on my %TEMP% in Windows – Space + Accents – Had to Set TEMP=D:Temp Deployment
- 65. 65/84 Doesn’t work in Cygwin – Packages not (yet?) available Break on my %TEMP% in Windows – Space + Accents – Had to Set TEMP=D:Temp Deployment
- 66. 66/84 Deployment Create a file apio.ini Generate and upload the bitstream [env] board = TinyFPGA-BX apio build apio upload
- 67. 67/84 Deployment Produces 3 files – Hardware.blif BLIF – Hardware.asc Place and route – Hardware.bin Bitstream apio build
- 69. 69/84 Deployment Asks for the boot-loader to be active Takes the bin file and apio upload
- 76. 76/84 State Machine A • LED <= 0 1 B • LED <= counter[...] 2 C • LED <= 1 3
- 77. 77/84 State Machine Must consider the speed of the FPGA 16Mhz 16 x 1,000 x 1,000 per second 27 bits register reg [26:0] counter; 24 bits, every 22nd bit
- 80. 80/84 CONCLUSION
- 81. 81/84 Okay But… TinyFPGA Bx Particle Photon
- 82. 82/84 Okay But… TinyFPGA Bx ICE40LP8K FPGA 6MB flash, 128KB RAM $54.72 HDL Verilog Many tools USB Particle Photon STM32 ARM Cortex M3 1MB flash, 128KB RAM $27.71 (Very) High-level APIs C Usual (?) compilers Over-the-air (WiFi)
- 83. 83/84 Okay But… Different applications – MCU: fix hardware, flexible “software” – FPGA: flexible hardware, flexible “software” Reimplementing a processor would be difficult (impossible) with a MCU https://www.quora.com/Should-I-learn-FPGA-or-STM32
- 84. 84/84 And More… How do we interconnect these with other sensors and actuators? How do we test such systems? How do we debug/update such systems?