Adder, Subtractor, Binary Parallel Adder, Decimal Adder, Magnitude Comparator and Decoder

1. Combinational Logic
By
Dr. Heman Pathak
Associate Professor
Dept. of Comp. Sc.
Kanya Gurukul Dehradun

2. Combinational Logic

3. Combinational Logic

4. Design Procedure
The Problem is Stated
The number of available input variables and required output variables is determined.
The input and output variables are assigned letter symbols.
The truth table that defines the required relationship between inputs and outputs is derived.
The simplified Boolean function for each output variable is obtained.
The logic diagram is drawn.

5. Adders

6. Half Adder
X Y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S’ = X’Y’ + XY C’ = X’ + Y’
S = (X’Y’ + XY)’ C = (X’ + Y’)’
S = (X + Y)(X’ + Y’) C = XY
Design a circuit for Half-Adder
Inputs -2 Outputs - 2
Inputs – x & y Outputs – S & C

7. Half Adder

8. Half Adder

9. Half Adder
S = (X’Y’ + XY)’
S = (X’Y’ + C)

10. Half Adder

11. Half Adder

12. Full Adder
Design a circuit for Full-Adder
Inputs -3 Outputs - 2
Inputs – x,y & z Outputs – S & C

13. Full Adder

14. Full Adder

15. Full Adder

16. Full Adder
LET A = X  Y = X’Y +XY’
X  Y  Z = A  Z
= A’Z + AZ’
= (X’Y+XY’)’ Z+ (X’Y+XY’)Z’
= (X +Y’)(X’+Y)Z + X’YZ’ + XY’Z’
= (XX’+XY+X’Y’+YY’)Z + X’YZ’+XY’Z’
= XYZ + X’Y’Z + X’YZ’ + XY’Z’
= m1 + m2 + m4 + m7
S = X  Y  Z

17. Full Adder
C = x’yz + xy’z + xyz’ + xyz
= z(x’y + xy’) + xy(z’ + z)
= z(x  y) + xy

18. Full Adder
C = x’yz + xy’z + xyz’ + xyz
= z(x’y + xy’) + xy(z’ + z)
= z(x  y) + xy

19. Half Subtrator
Design a circuit for Half Subtrator
Inputs -2 Outputs - 2
Inputs – x & y Outputs – D & B

20. Half Subtrator

21. Full Subtrator
Design a circuit for Full Subtrator
Inputs -3 Outputs - 2
Inputs – x & y Outputs – D & B

22. Full Subtrator

23. Full Subtrator

24. Full Subtrator

25. Full Subtrator

26. Binary Parallel Adder

27. Binary Parallel Adder

28. Subtraction by 2’s Complement

29. Subtraction by 2’s Complement

30. Subtraction by 2’s Complement
M = 4+16+64=84
N = 4+64 = 68
M-N = 16
N-M = -16

31. Subtraction by 2’s Complement

32. Subtraction by 2’s Complement
• A – B = A + (B’+1)
= A + B’ + (C0 = 1)
1

33. Binary Parallel Subtractor
S B F
0 0 0
0 1 1
1 0 1
1 1 0
F = S’B + SB’

34. Binary Parallel Adder/Subtractor

35. Carry Propagation
35

36. Boolean functions
Pi = Ai ⊕ Bi steady state value
Gi = AiBi steady state value
Output sum and carry
Si = Pi ⊕ Ci
Ci+1 = Gi + PiCi
Gi : carry generate Pi : carry propagate
36

37. • Delay time of n-bit CLAA = XOR + (AND + OR) + XOR

38. Binary Parallel Adder

39. Binary Coded Decimal (BCD)
BCD is a class of binary encodings of decimal numbers
where each digit is represented by a four bits.
Decimal
Digit
BCD/
Binary
Decimal
Digit
Binary BCD
0 0000 10 1010 0001 0000
1 0001 11 1011 0001 0001
2 0010 15 1111 0001 0101
3 0011 16 10000 0001 0110
4 0100 17 10001 0001 0111
5 0101 18 10010 0001 1000
6 0110 19 10011 0001 1001
7 0111 20 10100 0010 0000
8 1000 29 11101 0010 1001
9 1001 64 1000000 0110 0100

40. Binary Coded Decimal (BCD)
Design a Decimal Adder
Input - 9 Output - 5
Input – A,B,Cin Output – Z,Cout

42. Decimal Adder
• When the binary sum is greater than 1001, we obtain
a non-valid BCD representation.
• The addition of binary 6(0110) to the binary sum
converts it to the correct BCD representation and also
produces an output carry as required.
C = K + Z8Z4 + Z8Z2

44. Decimal Adder

45. Decimal Adder

46. Magnitude Comparator
46

47. Magnitude Comparator
47

48. Magnitude Comparator
48
A B X
0 0 1
0 1 0
1 0 0
1 1 1
X = A’B’ + AB
X = A’B’ + AB = A XNOR B
X = (A XOR B)’
= (A’B + AB’)’
= (A’B)’. (AB’)’
= (A + B’).(A’ + B)
= AA’ + AB + A’B’ + BB’
= AB + A’B’

49. Magnitude Comparator
49

50. Magnitude Comparator
50

51. Magnitude Comparator
51
We inspect the relative magnitudes of
pairs of MSB. If equal, we compare
the next lower significant pair of
digits until a pair of unequal digits is
reached.
If the corresponding digit of A is 1
and that of B is 0, we conclude that
A>B.
(A>B)=A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0
(A<B)=A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0

52. Decoders
• The decoder is called n-to-m-line decoder, where
m≤2n
.
• the decoder is also used in conjunction with other
code converters such as a BCD-to-seven_segment
decoder.
• 3-to-8 line decoder: For each possible input
combination, there are seven outputs that are equal
to 0 and only one that is equal to 1.
52

53. Decoders
53
A B Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
No. of Inputs = n
No. of Possible Combinations = 2n
No. of Outputs ≤ 2n

54. Decoders (3 X 8)
54
No. of Inputs = 3
No. of Possible Combinations = 23
No. of Outputs = 8

55. Decoders (3 X 8)
55

56. Decoders (BCD-to-Decimal)
56

57. Decoders (BCD-to-Decimal)
57
w x y z D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

58. Decoders (BCD-to-Decimal)
58
w x y z D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
1 0 1 0 X X X X X X X X X X
1 0 1 1 X X X X X X X X X X
1 1 0 0 X X X X X X X X X X
1 1 0 1 X X X X X X X X X X
1 1 1 0 X X X X X X X X X X
1 1 1 1 X X X X X X X X X X

59. Decoders (BCD-to-Decimal)
59
YZ 00 01 11 10
00 1 0 0 0
01 0 0 0 0
11 X X X X
10 0 0 X X
WX

60. Decoders (BCD-to-Decimal)
60

61. 61

62. Decoders (BCD-to-Decimal)
62

63. Decoders (3 X 8)
63

64. Decoders

65. Decoders

66. Decoders

67. Decoder with Enable input
A B Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
E A B Q0 Q1 Q2 Q3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

68. Decoder with Enable input

69. Decoder with Enable input
X’/E A/Y B/Z Q0 Q1 Q2 Q3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
X/E A/Y B/Z Q4 Q5 Q6 Q7
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
X Y Z Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

70. Decoder with Enable input
X
Y
Z

71. Decoder with Enable input

72. Decoder using NAND Gates
E A B D0 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

73. Decoder using NAND Gates