UNIT-2.pptx

MEDI-CAPS UNIVERSITY
Faculty of Engineering
Mr. Sagar Pandya
Information Technology Department
sagar.pandya@medicaps.ac.in

Computer System Architecture
Mr. Sagar Pandya
Information Technology Department
Course
Code
Course Name Hours Per
Week
Total Hrs. Total
Credits
L T P
IT3CO20 Computer System Architecture 3 1 2 6 5

Reference Books
 Text Book:
1. Computer System Architecture by Mano, M.M.,, Prentice Hall of India
2. Computer Organization and Architecture, Stallings William, Prentice Hall of
India
3. Computer Architecture and Organization, by Hayes, J.P.,McGraw,Hill
 Reference Books:
1. Computer Organization by V. Carl Hamacher, Safwat G. Zaky and Zvonko G.
Vranesic , McGraw,Hill series
2. Computer Organization and Design, by David Patterson and John Hennessey,”
Elsevier.
3. Computer Systems Design and Architecture (2nd Edition) by Vincent P.
Heuring and Harry F. Jordan etc.
Mr. Sagar Pandya

Unit-2
 Addressing Modes,
 Direct and Indirect Address,
 Arithmetic Logic Units control and data path,
 Data path components,
 Design of ALU and data path,
 Stack Organization,
 Discussions about RISC versus CISC architectures,
 Controller design,
 Hardwired and Micro programmed Control.
Mr. Sagar Pandya

INTRODUCTION
 The operation field of an instruction specifies the operation to be
performed.
 This operation must be executed on some data stored in computer
registers or memory words.
 The way the operands are chosen during program execution is
dependent on the addressing mode of the instruction.
 The addressing mode specifies a rule for interpreting or modifying
the address field of the instruction before the operand is actually
referenced.
 Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
Mr. Sagar Pandya

ADDRESSING MODES
 1. To give programming versatility to the user by providing such
facilities as pointers to memory, counters for loop control, indexing
of data, and program relocation.
 2. To reduce the number of bits in the addressing field of the
instruction.
 The availability of the addressing modes gives the experienced
assembly language programmer flexibility for writing programs that
are more efficient with respect to the number of instructions and
execution time.
 To understand the various addressing modes to be presented in this
section, it is imperative that we understand the basic operation cycle
of the computer.
Mr. Sagar Pandya

ADDRESSING MODES
 The control unit of a computer is designed to go through an
instruction cycle that is divided into three major phases:
 1. Fetch the instruction from memory.
 2. Decode the instruction.
 3. Execute the instruction
 The operation field of an instruction specifies the operation to be
performed.
 This operation will be executed on some data which is stored in
computer registers or the main memory.
 The way any operand is selected during the program execution is
dependent on the addressing mode of the instruction.
Mr. Sagar Pandya

ADDRESSING MODES
 Addressing Modes– The term addressing modes refers to the way in
which the operand of an instruction is specified.
 The addressing mode specifies a rule for interpreting or modifying
the address field of the instruction before the operand is actually
executed.
 The purpose of using addressing modes is as follows:
 To give the programming versatility to the user.
 To reduce the number of bits in addressing field of instruction.
 An assembly language program instruction consists of two parts
Mr. Sagar Pandya

ADDRESSING MODES
 IMPORTANT TERMS
 Starting address of memory segment.
 Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and
index.
 Displacement: It is an 8 bit or 16 bit immediate value given in the
instruction.
 Base: Contents of base register, BX or BP.
 Index: Content of index register SI or DI.
 According to different ways of specifying an operand by 8086
microprocessor, different addressing modes are used by 8086.
Mr. Sagar Pandya

ADDRESSING MODES
 1.) Implied mode: In implied addressing the operand is specified in
the instruction itself.
 In this mode the data is 8 bits or 16 bits long and data is the part of
instruction.
 Zero address instruction are designed with implied addressing mode.
 Example: CLC (used to reset Carry flag to 0), CLA, INCA.
Mr. Sagar Pandya

ADDRESSING MODES
 2.) Immediate addressing mode
 Operand is part of instruction
 Operand = address field
 e.g. ADD AX, 5h
 LDA #5
 Add 5 to contents of accumulator
 5 is operand
 No memory reference to fetch data
 Fast
 Limited range
Mr. Sagar Pandya

ADDRESSING MODES
 Immediate addressing mode (symbol #):
 In this mode data is present in address field of instruction .
 Designed like one address instruction format.
 Note: Limitation in the immediate mode is that the range of constants
are restricted by size of address field.
 Example: MOV AL, 35H (move the data 35H into AL register)
Mr. Sagar Pandya

ADDRESSING MODES
 3.) Register Addressing
 In register addressing mode, the operand is placed in one of 8 bit or
16 bit general purpose register.
 Register Number written in Instruction.
 Operand is held in register named in address filed
 EA = R
 Limited number of registers
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
 MOV AX, BX
 ADD AX, BX
Mr. Sagar Pandya

ADDRESSING MODES
 No memory access
 Very fast execution
 Very limited address space
Mr. Sagar Pandya

ADDRESSING MODES
 Advantages
 Shorter instructions and faster instruction fetch.
 Faster memory access to the operand(s)
 Disadvantages
 Very limited address space
 Using multiple registers helps performance but it complicates the
instructions.
Mr. Sagar Pandya

ADDRESSING MODES
 4.) Register Indirect Mode
 In register indirect addressing mode, the address of operand is placed
in any one of the registers.
 The instruction specifies a register that contains the address of the
operand.
 Register indirect addressing mode also used to call as indirect
addressing mode.
 Example:- LD (R1)
 AC M[(R1)]
Mr. Sagar Pandya

ADDRESSING MODES
 Example:
 ADD R1,(R2)
 R1R1+M[(R2)]
Mr. Sagar Pandya

ADDRESSING MODES
S.no. REGISTER MODE REGISTER INDIRECT MODE
1 Operand is placed in general
purpose register.
Operand’s offset is placed in one of the
registers.
2 In register mode, address field
contains the effective address of
operand.
In register indirect mode, address field
contains reference of effective address.
3 It requires only one register
reference to access data.
It requires two register references to
access data.
4 No further calculation is required
to perform the operation.
Require further calculation to find the
effective address.
5 Register addressing mode is fast. register indirect addressing mode is slow.
Mr. Sagar Pandya

ADDRESSING MODES
Mr. Sagar Pandya
 5.) Auto Indexed (Auto Increment/ Decrement Mode)
 In this the register is incremented or decremented after or before its
value is used.
 It is a special case of Register Indirect Addressing Mode.
 Auto Increment Mode:
 Effective address of the operand is the contents of a register specified
in the instruction.
 After accessing the operand, the contents of this register are
automatically incremented to point to the next consecutive memory
location.(R1)+.
 Here one register reference, one memory reference and one ALU
operation is required to access the data.

ADDRESSING MODES
Mr. Sagar Pandya
 Example:
 Add R1, (R2)+ // OR
 R1 = R1 +M[R2]
 R2 = R2 + d
 Useful for stepping through arrays in a loop. R2 – start of array d –
size of an element.
 Auto Decrement Mode:
 Effective address of the operand is the contents of a register specified
in the instruction. Before accessing the operand, the contents of this
register are automatically decremented to point to the previous
consecutive memory location. –(R1)
 Here one register reference, one memory reference and one ALU
operation is required to access the data.

ADDRESSING MODES
Mr. Sagar Pandya
 Example:
 Add R1,-(R2) //OR
 R2 = R2-d
 R1 = R1 + M[R2]
 Auto decrement mode is same as auto increment mode.
 Both can also be used to implement a stack as push and pop .
 Auto increment and Auto decrement modes are useful for
implementing “Last-In-First-Out” data structures.

ADDRESSING MODES
Mr. Sagar Pandya
 6.) Direct Addressing Mode /Absolute addressing Mode
 In this mode, effective address of operand is present in instruction itself.
 No additional calculations to find the effective address of the operand.
 For Example: ADD R1, 4000 - In this the 4000 is effective address of
operand.
 NOTE: Effective Address is the location where operand is present.

ADDRESSING MODES
Mr. Sagar Pandya
 Address field contains address of operand
 Effective address EA = address field (A)
 ADD AX, value
 Value DB 05h
 Add contents of cell value to accumulator AX
 Look in memory at address value for operand.
 Single memory reference to access data
 No additional calculations to work out effective address
 Limited address space

ADDRESSING MODES
Mr. Sagar Pandya
 7.) Indirect Addressing Mode
 In this, the address field of instruction gives the address where the
effective address is stored in memory.
 This slows down the execution, as this includes multiple memory
lookups to find the operand.
 In this mode address field of instruction contains the address of
effective address. Here two references are required.
 1st reference to get effective address.
 2nd reference to access the data.
 Based on the availability of Effective address, Indirect mode is of
two kind:

ADDRESSING MODES
Mr. Sagar Pandya
 1. Register Indirect: In this mode effective address is in the register,
and corresponding register name will be maintained in the address
field of an instruction.
 Here one register reference, one memory reference is required to
access the data.

ADDRESSING MODES
Mr. Sagar Pandya
 2. Memory Indirect: In this mode effective address is in the memory,
and corresponding memory address will be maintained in the
address field of an instruction.
 Here two memory reference is required to access the data.

ADDRESSING MODES
Mr. Sagar Pandya
 8.) Displacement Addressing Mode
 In this the contents of the indexed register is added to the Address
part of the instruction, to obtain the effective address of operand.
 EA = A + (R), In this the address field holds two values, A(which is
the base value) and R(that holds the displacement), or vice versa.
 Effective address=start address + displacement
 Effective address=Offset + (Segment Register)
 Use direct and register indirect
 Address field hold two values
 A = base value
 R = register that holds displacement or vice versa

ADDRESSING MODES
Mr. Sagar Pandya

ADDRESSING MODES
Mr. Sagar Pandya
 9.) Relative Addressing Mode:
 In this addressing mode, Effective address of the operand is obtained
by adding the content of program counter with the address part of
the instruction.
 A version of displacement addressing.
 R = Program counter, PC
 EA = A + (PC)
 Effective Address = Content of Program Counter + Address part of
the instruction (Offset)

ADDRESSING MODES
Mr. Sagar Pandya
 10.) Indexed Addressing Mode
by adding the content of index register with the address part of the
instruction.
 Effective Address = Content of Index Register + Address part of the
instruction
 Index addressing mode is helpful when the instructions in the
program are accessing the array or the large range of memory
addresses.
 In this mode, the effective address is generated by adding a constant
to the register’s content. The content of the register does not change.

ADDRESSING MODES
Mr. Sagar Pandya
 11.) Base Register Addressing Mode
by adding the content of base register with the address part of the
instruction.
 Used in Program Relocation
 Effective Address = Content of Base Register + Address part of the
instruction (Displacement)
 We give Displacement rather than Absolute Address.

ADDRESSING MODES
Mr. Sagar Pandya
 12. ) Stack Addressing Mode
 Operand is (implicitly) on top of stack
 e.g. ADD Pop top two items from stack and add and push

Mr. Sagar Pandya
Address Memory
100 Load to AC Mode
101 Address 400
102 Next Instruction
209 450
300 600
399 555
400 700
500 800
502 75
600 225
700 200
R1 400
XR (Index Register) 100
BR (Base Register) 200

ADDRESSING MODES - Numerical
Mr. Sagar Pandya
 An instruction is stored at location 300 with its address field at
location 301.The address field has the value 400. A processor
register R1 contains the number 200. Evaluate the effective address
if the addressing mode of the instruction is
 (a) Direct
 (b) Immediate
 (c) Relative
 (d) Register Indirect

ADDRESSING MODES
Mr. Sagar Pandya
 (a) direct addressing:- Direct addressing means that the address field
contains the address of memory location the instruction is supposed
to work with (where an operand "resides"). Effective address would
therefore be 400.
 (b) immediate addressing:- Immediate addressing means that the
address field contains the operand itself. Effective address would
therefore be 301.
 (c) relative addressing:- Relative addressing means that the address
field contains offset to be added to the program counter to address a
memory location of the operand. Effective address would therefore
be 301 + 400 = 701.
 (d) register indirect addressing:- Register indirect addressing means
that the address of an operand is in the register. Effective address
would be 200.

ALU and Datapath
Mr. Sagar Pandya
 Inside a computer, there is an Arithmetic Logic Unit (ALU), which
is capable of performing logical operations (e.g. AND, OR, Ex-OR,
Invert etc.) in addition to the arithmetic operations (e.g. Addition,
Subtraction etc.).
 The control unit supplies the data required by the ALU from
memory, or from input devices, and directs the ALU to perform a
specific operation based on the instruction fetched from the memory.
 ALU is the “calculator” portion of the computer.
 An arithmetic logic unit(ALU) is a major component of the central
processing unit of the a computer system.
 It does all processes related to arithmetic and logic operations that
need to be done on instruction words.

ALU and Datapath
Mr. Sagar Pandya
 In some microprocessor architectures, the ALU is divided into the
arithmetic unit (AU) and the logic unit (LU).
 ALU is also known as an Integer Unit (IU).
 The arithmetic logic unit is that part of the CPU that handles all the
calculations the CPU may need.
 Most of these operations are logical in nature.
 Depending on how the ALU is designed, it can make the CPU more
powerful, but it also consumes more energy and creates more heat.
 Therefore, there must be a balance between how powerful and
complex the ALU is and how expensive the whole unit becomes.
This is why faster CPUs are more expensive, consume more power
and dissipate more heat.

ALU and Datapath
Mr. Sagar Pandya
 Different operation as carried out by ALU can be categorized as
follows –
 Logical operations − These include operations like AND, OR, NOT,
XOR, NOR, NAND, etc.
 Bit-Shifting Operations − This pertains to shifting the positions of
the bits by a certain number of places either towards the right or left,
which is considered a multiplication or division operations.
 Arithmetic operations − This refers to bit addition and subtraction.
Although multiplication and division are sometimes used, these
operations are more expensive to make.
 Multiplication and subtraction can also be done by repetitive
additions and subtractions respectively.

ALU and Datapath
Mr. Sagar Pandya

ALU and Datapath
Mr. Sagar Pandya
 The ALU is a digital circuit that provides arithmetic and logic
operation.
 It is the fundamental building block of central processing unit of a
computer.
 A modern CPU has very powerful ALU and it is complex in design. In
addition to ALU modern CPU contains control unit and set of registers.
 Most of the operations are performed by one or more ALU’s, which
load data from input register. Registers are a small amount of storage
available to CPU.
 These registers can be accessed very fast. The control unit tells ALU
what operation to perform on the available data. After
calculation/manipulation the ALU stores the output in an output register.

ALU and Datapath
Mr. Sagar Pandya
 What is the Data path?
 Suppose any data processing operation should be performed in the CPU
like transferring the content of register from one place to another, from one
register to another register, performing the addition of two numbers in
ALU, copying something in memory and copying to register.
 So, any data processing operation happens in the CPU, then for that data
operation, data follows a specific path, which is called “data path.”
 “Data path is the collection of functional units such as arithmetic logic
units or multipliers. Data path is required to perform data processing
operations.”
 To perform any operation in the CPU, data follows a specific path within
the CPU to execute the instruction. That followed path is known as a data
path.

ALU and Datapath
Mr. Sagar Pandya
 The CPU can be divided into two section: data section and control section. The
DATA section is also known as data path.
 IRPC
 1) PCAR
 2) IRM[AR], PCPC+1
 BUS:
 In early computers “BUS” were parallel electrical wires with multiple
hardware connections.
 Therefore a bus is communication system that transfers data between
component inside a computer, or between computers.
 It includes hardware components like wires, optical fibers, etc and software,
including communication protocols.
 The Registers, ALU and the interconnecting BUS are collectively referred as
data path.

ALU and Datapath
Mr. Sagar Pandya
 Types of bus are:
 Address bus: The buses which are used to carry address.
 Data bus: The buses which are used to carry data.
 Control bus: If the bus is carrying control signals .
 Power bus: If it is carrying clock pulse, power signals it is known as
power bus, and so on.
 The bus can be dedicated, i.e., it can be used for a single purpose or it
can be multiplexed, i.e., it can be used for multiple purpose.
 When we would have different kinds of buses, different types of bus
organization will take place.

ALU and Datapath
Mr. Sagar Pandya
 PC (Program Counter): Holds the address of the next instruction
 IR (Instruction Register): Holds the executing instruction
 Instruction Cache: ‘Fast’ memory where the next instruction comes
from Reg[index]
 (Register File): Contains the 32 registers
 Arithmetic Logic Unit (ALU): Performs all arithmetic operations
 Data Cache: Data read from or written to ‘fast’ memory
 Multiplexer: Multiple inputs selects one output based upon control
signal(s).

ALU and Datapath
Mr. Sagar Pandya
 Single-Cycle Data Path:
 Each instruction executes in one clock cycle
 Every cycle must be equal length
 The cycle time must be long enough to accommodate the longest
instruction.
 Multi-Cycle Data Path:
 Each instruction takes multiple clock cycles
 Have the cycle time coincide with the instruction stage time.
 Cycle time = 2 ns (time of longest stage)
 Between stages we need registers to hold data for next stage.

ALU and Datapath
Mr. Sagar Pandya
 One-Bus Organization
 In one bus organization, a single bus is used for multiple purpose.
 A set of general purpose register, program counter, instruction
register, memory address register(MAR), memory data
register(MDR) are connected with the single bus.
 Memory read/write can be done with MAR and MDR.
 The program counter points to the memory location from where the
next instruction is to be fetched.
 Instruction register is that every register will hold the copy of the
current instruction.
 In case of one bus organization, at a time only one operand can be
read from the bus.

ALU and Datapath
Mr. Sagar Pandya
 One-Bus Organization
 As a result of that, if the requirement is to read two operand for the
operation then read operation need to be carried twice.
 So that’s why it is making the process little longer.
 One of the advantage of one bus organization is that, it is one of the
simplest and also this is very cheap to implement.
 At the same time a disadvantage lies that it has only one bus and this
“one bus” is accessed by all general purpose registers, program
counter, instruction register, MAR, MDR making each and every
operation sequential.
 No one recommend this architecture now-a-days.

ALU and Datapath
Mr. Sagar Pandya
 Two-Bus Organization
 Two overcome the disadvantage of one bus organization an another
architecture was developed known as two bus organization.
 In two bus organization there are two buses.
 The general purpose register can read/write from both the buses.
 In this case, two operands can be fetched at the same time because
of the two buses.
 One of bus fetch operand for ALU and another bus fetch for register.
 The situation arises when both buses are busy fetching operands,
output can be stored in temporary register and when the buses are
free, particular output can be dumped on the buses.

ALU and Datapath
Mr. Sagar Pandya
 Two-Bus Organization
 General-purpose registers are connected to both buses.
 Data can be transferred from two different registers to the input
point of the ALU at the same time.
 Two operand operation can fetch both operands in the same clock
cycle.
 There are two versions of two bus organization, i.e., in-bus and out-
bus.
 From in-bus the general purpose register can read data and to the out
bus the general purpose registers can write data.

ALU and Datapath
Mr. Sagar Pandya
 Three-Bus Organization
 In three bus organization we have three bus, OUT bus1, OUT bus2
and a IN bus.
 From the out buses we can get the operand which can come from
general purpose register and evaluated in ALU and the output is
dropped on In Bus so it can be sent to respective registers.
 This implementation is a bit complex but faster in nature because in
parallel two operands can flow into ALU and out of ALU.
 It was developed to overcome the “busy waiting” problem of two
bus organisation.
 In this structure after execution, the output can be dropped on the
bus without waiting because of presence of an extra bus.

ALU and Datapath
Mr. Sagar Pandya
 Three-Bus Organization
 Two buses may be used as source buses while the third is used as
destination.
 The source buses move data out of registers (out-bus), and the
destination bus may move data into a register (in-bus).
 Each of the two out-buses is connected to an ALU input point. The
output of the ALU is connected directly to the in-bus
 Increasing the number of buses will also increase the complexity of
the hardware.

ALU and Datapath
Mr. Sagar Pandya
 The main advantages of multiple bus organizations over single bus
are as given below.
1. Increase in size of the registers.
2. Reduction in the number of cycles for execution.
3. Increases the speed of execution or we can say faster execution.

Stack Organization
Mr. Sagar Pandya
 A useful feature that is included in the CPU of most computers is a
stack or last-in, first-out (LIFO) list.
 A stack is a storage device that stores information in such a manner
that the item stored last is the first item retrieved.
 The operation of a stack can be compared to a stack of trays.
 The last tray placed on top of the stack is the first to be taken off.
 The stack in digital computers is essentially a memory unit with an
address register that can count only (after an initial value is loaded
into it).
 The register that holds the address for the stack is called a stack
pointer (SP) because its value always points at the top item in the
stack.

Stack Organization
Mr. Sagar Pandya
 Contrary to a stack of trays where the tray itself may be taken out or
inserted, the physical registers of a stack are always available for
reading or writing.
 It is the content of the word that is inserted or deleted.
 The two operations of a stack are the insertion and deletion of items.
 The operation of insertion is called push (or push-down) because it can
be thought of as the result of pushing a new item on top.
 The operation of deletion is called pop (or pop-up) because it can be
thought of as the result of removing one item so that the stack pops up.
 However, nothing is pushed or popped in a computer stack.
 These operations are simulated by incrementing or decrementing the
stack pointer register.

Stack Organization
Mr. Sagar Pandya
 1.) Register Stack
 A stack can be placed in a portion of a large memory or it can be
organized as a collection of a finite number of memory words or
registers.
 The stack pointer register SP contains a binary number whose value is
equal to the address of the word that is currently on top of the stack.
 Three items are placed in the stack: A, B, and C, in that order.
 Item C is on top of the stack so that the content of SP is now 3.
 To remove the top item, the stack is popped by reading the memory
word at address 3 and decrementing the content of SP.
 Item B is now on top of the stack since SP holds address 2.

Stack Organization
Mr. Sagar Pandya
 To insert a new item, the stack is pushed by incrementing SP and
writing a word in the next-higher location in the stack.
 Note that item C has been read out but not physically removed.
 This does not matter because when the stack is pushed, a new item is
written in its place.
 In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
 Since SP has only six bits, it cannot exceed a number greater than 63
(111111 in binary).
 When63 is incremented by 1, the result is 0 since 111111 + 1 = 1000000
in binary, but SP can accommodate only the six least significant bits.
 Similarly, when 000000 is decremented by 1, the result is 111111.

Stack Organization
Mr. Sagar Pandya
 The one-bit register FULL is set to 1 when the stack is full, and the
one-bit register EMTY is set to 1 when the stack is empty of items.
 DR is the data register that holds the binary data to be written into or
read out of the stack.
 Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0,
so that SP points to the word at address 0 and the stack is marked empty
and not full.
 If the stack is not full (if FULL = 0), a new item is inserted with a push
operation.
 The stack pointer is incremented so that it points to the address of the
next-higher word.
 A memory write operation inserts the word from DR into the top of the
stack.

Stack Organization
Mr. Sagar Pandya
 Note that SP holds the address of the top of the stack and that M[SP]
denotes the memory word specified by the address presently available
in SP.
 The first item stored in the stack is at address L The last item is stored
at address 0.
 If SP reaches 0, the stack is full of items, so FULL is set to L This
condition is reached if the top item prior to the last push was in location
63 and, after incrementing SP, the last item is stored in location 0.
 Once an item is stored in location 0, there are no more empty registers
in the stack.
 If an item is written in the stack, obviously the stack cannot be empty,
so EMTY is cleared to 0.

Stack Organization
Mr. Sagar Pandya
 SP  SP + 1 Increment stack pointer
 M[SP]  DR Write item on top of the stack
 If (SP = 0) then (FULL  1) Check if stack is full
 EMTY  0 Mark the stack not empty

Stack Organization
Mr. Sagar Pandya
 DR M[SP] Read item from the top of stack
 SP  SP – 1 Decrement stack pointer
 If (SP = 0) then (EMTY  1) Check if stack is empty
 FULL  0 Mark the stack not full

Stack Organization
Mr. Sagar Pandya
 2.) Memory Stack
 A stack can exist as a stand-alone unit as in Fig. or can be implemented
in a random-access memory attached to a CPU.
 The implementation of a stack in the CPU is done by assigning a
portion of memory to a stack operation and using a processor register as
a stack pointer.
 Figure shows a portion of computer memory partitioned into three
segments: program, data, and stack.
 The program counter PC points at the address of the next instruction in
the program.
 The address register AR points at an array of data.
 The stack pointer SP points at the top of the stack.

Stack Organization
Mr. Sagar Pandya
 The three registers are connected to a common address bus, and either
one can provide an address for memory.
 PC is used during the fetch phase to read an instruction.
 AR is used during the execute phase to read an operand.
 SP is used to push or pop items into or from the stack.
 As shown in Fig., the initial value of SP is 4001 and the stack grows
with decreasing addresses.
 Thus the first item stored in the stack is at address 4000, the second
item is stored at address 3999, and the last address that can be used for
the stack Is 3000.
 No provisions are available for stack limit checks.

Stack Organization
Mr. Sagar Pandya
 A new item is inserted with
 a push operation as follows:
 SP  SP - 1
 M[SP]  DR
 A new item is deleted with
 a pop operation as follows:
 DR  M[SP]
 SP  SP + 1

Stack Organization
Mr. Sagar Pandya
 The top item is read from the stack into DR.
 The stack pointer is then incremented to point at the next item in the
stack.
 Most computers do not provide hardware to check for stack overflow
(full stack) or underflow (empty stack).
 The stack limits can be checked by using two processor registers.
 one to hold the upper limit (3000 in this case), and the other to hold
the lower limit (4001 in this case).
 After a push operation, SP is compared with the upper-limit register
and after a pop operation, SP is compared with the lower-limit
register.

RISC and CISC
Mr. Sagar Pandya
 A microprocessor is a processing unit on a single chip.
 It is an integrated circuit which performs the core functions of a
computer CPU.
 It is a multipurpose programmable silicon chip constructed using
Metal Oxide Semiconductor (MOS) technology which is clock
driven and register based.
 It accepts binary data as input and provides output after processing it
as per the specification of instructions stored in the memory.
 These microprocessors are capable of processing 128 bits at a time at
the speed of one billion instructions per second.
 Besides the classification based on the word length, the classification
is also based on the architecture i.e. Instruction Set of the
microprocessor. These are categorized into RISC and CISC.

RISC and CISC
Mr. Sagar Pandya
 Reduced Instruction Set Computer (RISC):
 A reduced instruction set computer is a computer that only uses
simple commands that can be divided into several instructions that
achieve low-level operation within a single CLK cycle, as its name
proposes “Reduced Instruction Set”.

RISC and CISC
Mr. Sagar Pandya
 The RISC is a Reduced Instruction Set Computer microprocessor
and its architecture includes a set of instructions that are highly
customized.
 The main function of this is to reduce the time of instruction
execution by limiting as well as optimizing the number of
commands.
 So each command cycle uses a single clock cycle where every clock
cycle includes three parameters namely fetch, decode & execute.
 The kind of processor is mainly used to execute several difficult
commands by merging them into simpler ones.
 RISC processor needs a number of transistors to design and it
reduces the instruction time for execution.

RISC and CISC
Mr. Sagar Pandya
 Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeline can be achieved.
 Examples of RISC processors
 MIPS, SPARC, IBM POWER instruction set, Alpha, RISC-V, ARM
architecture.

RISC and CISC
Mr. Sagar Pandya
 RISC Processor Architecture (Block diagram)
 RISC processor is implemented using the hardwired control unit.
 The hardwired control unit produces control signals which regulate
the working of processors hardware.
 RISC architecture emphasizes on using the registers rather than
memory.
 This is because the registers are the ‘fastest’ available memory
source.
 The registers are physically small and are placed on the same chip
where the ALU and the control unit are placed on the processor.
 The RISC instructions operate on the operands present in processor’s
registers.

RISC and CISC
Mr. Sagar Pandya

RISC and CISC
Mr. Sagar Pandya
 Advantages of RISC Processor
1. RISC instructions are simpler machine instruction.
2. RISC instructions are hardwired to fasten the execution.
3. There are very fewer instructions in s RISC instruction set.
4. RISC instruction has simple addressing modes.
5. RISC instruction executes faster because most of instruction
operates on processor register and there is no need to access
memory for each instruction.
6. It is easy to pipeline RISC instruction as all instruction is of fixed
size and opcode and operand are located in the same position in the
word.
7. RISC instructions execute one instruction per clock cycle.

RISC and CISC
Mr. Sagar Pandya
 Disadvantages of RISC Processor
1. RISC instruction size is reduced but more instructions are required
to perform an operation when compared with CISC. So, we can say
that the length of the program is increased.
2. The machine instructions are hardwired in RISC so, it would cost if
any instruction needs modification.
3. It finds is difficulty in processing complex instruction and complex
addressing mode.
4. RISC instructions do not allow direct memory to memory transfer,
it requires Load and Store instructions to do so.

RISC and CISC
Mr. Sagar Pandya
 Complex Instruction Set Computer (CISC)
 It was developed by the Intel Corporation and it is Complex
Instruction Set Computer.
 This processor includes a huge collection of simple to complex
instructions.
 These instructions are specified in the level of assembly language
level and the execution of these instructions takes more time.
 CISC processors were evolved in the 1970s before the evolution of
RISC (Reduced Instruction Set Computers) processors.
 During this period the computer memory uses to be ‘small’ and ‘very
expensive’.

RISC and CISC
Mr. Sagar Pandya
 CISC processors were helpful in simplifying the code and making it
shorter in order to reduce the memory requirement.
 In a CISC processor, a single instruction has ‘several low-level
operations’. This makes the CISC instructions short but ‘complex’.
 So, this processor moves to decrease the number of instructions on
every program & ignore the number of cycles for each instruction.
 It highlights to assemble complex instructions openly within the
hardware as the hardware is always as compared with software.
 However, CISC chips are relatively slower as compared to RISC
chips but utilize small instruction as compare with RISC.
 The best examples of the CISC processor include AMD, VAX,
System/360 & Intel x86.

RISC and CISC
Mr. Sagar Pandya
 Characteristics of CISC Processor
1. The length of the code is shorts, so it requires very little RAM.
2. CISC or complex instructions may take longer than a single clock cycle to
execute the code.
3. Less instruction is needed to write an application.
4. It provides easier programming in assembly language.
5. Support for complex data structure and easy compilation of high-level
languages.
6. It is composed of fewer registers and more addressing nodes, typically 5 to 20.
7. Instructions can be larger than a single word.
8. It emphasizes the building of instruction on hardware because it is faster to
create than the software.

RISC and CISC
Mr. Sagar Pandya
 CISC Processors Architecture
 As we have studied above the main objective of a CISC processor is
to minimize the program size by reducing the number of instructions
in a program.
 This is done by ’embedding some of the low-level instructions in a
single complex instruction’.
 Later when decoded this instruction generates several
microinstructions to execute.
 Now if a program/software is getting simplified then the hardware
has to get on work and must be able to perform the complex tasks.
 That’s why a CISC processor has complex hardware.

RISC and CISC
Mr. Sagar Pandya
 Here, a special microprogram control unit that uses a series of
microinstructions of the microprogram stored in the “control
memory” of the microprogram control unit and generate the control
signals.
 The control units access the control signals produced by the
microprogram control unit & operate the functioning of processors
hardware.
 Instruction and data path fetches the opcode and operands of the
instructions from the memory.
 Cache and main memory is the location where the program
instructions and operands are stored.

RISC and CISC
Mr. Sagar Pandya
 Advantages and Disadvantages of CISC Processors
 Advantages:
1. The code size is comparatively shorter which minimizes the
memory requirement.
2. Execution of a single instruction accomplishes several low-level
tasks.
3. Complex addressing mode makes the memory access flexible.
4. CISC instruction can directly access memory locations.

RISC and CISC
Mr. Sagar Pandya
 Disadvantages of CISC Processors
1. CISC chips are slower than RSIC chips to execute per instruction
cycle on each program.
2. The performance of the machine decreases due to the slowness of
the clock speed.
3. Executing the pipeline in the CISC processor makes it complicated
to use.
4. The CISC chips require more transistors as compared to RISC
design.
5. In CISC it uses only 20% of existing instructions in a programming
event.

RISC and CISC
Mr. Sagar Pandya
 Example – Suppose we have to add two 8-bit number:
 CISC approach: There will be a single command or instruction for
this like ADD which will perform the task.
 RISC approach: Here programmer will write first load command to
load data in registers then it will use suitable operator and then it will
store result in desired location.
 So, add operation is divided into parts i.e. load, operate, store due to
which RISC programs are longer and require more memory to get
stored but require less transistors due to less complex command.

RISC vs CISC
Mr. Sagar Pandya
S.No RISC CISC
1 Focus on software Focus on hardware
2
Uses only Hardwired control unit
Uses both hardwired and micro
programmed control unit
3 Transistors are used for more
registers
Transistors are used for storing
complex Instructions
4 Fixed sized instructions Variable sized instructions
5 Can perform only Register to
Register Arithmetic operations
Can perform REG to REG or REG
to MEM or MEM to MEM

RISC vs CISC
Mr. Sagar Pandya
S.No RISC CISC
6 Requires more number of registers Requires less number of registers
7 Code size is large Code size is small
8 A instruction execute in single
clock cycle
Instruction take more than one
clock cycle
9
A instruction fit in one word
Instruction are larger than size of
one word
10 RISC architecture is used in high-
end applications such as video
processing, telecommunications,
and image processing.
CISC architecture is used in low-
end applications such as security
systems, home automation, etc.

Controller Design
Mr. Sagar Pandya
 Design of Control Unit
 The Control Unit is classified into two major categories:
1. Hardwired Control
2. Microprogrammed Control
 Both Hardwired and Microprogrammed control unit was designed to
‘generate’ the control signals.
 The control signals operate the functioning of the processor’s
hardware.
 It decides what operation has to be performed, what must be the
sequence of the operations performed by the processor, in what time
an operation must be executed and so on.

Controller Design
Mr. Sagar Pandya

Controller Design
Mr. Sagar Pandya
 Control unit generates timing and control signals for the operations
of the computer.
 The control unit communicates with ALU and main memory.
 It also controls the transmission between processor, memory and the
various peripherals. It also instructs the ALU which operation has to
be performed on data.
 What is Hardwired Control Unit?
 In simple words, the hardwired control unit generates the control
signals to execute the instructions in a proper sequence and at the
correct time.
 The hardwired control unit is created with the hardware; it is a
circuitry approach. It is designed for the RISC style instruction set.

Hardwired Control Unit
Mr. Sagar Pandya
 The instruction register is a processors register that has the
‘instruction’ which is currently in execution.
 The instruction register generates the OP-code bits respective of the
operation and the addressing modes of the operands, mentioned in
the instruction.
 Instruction decoder receives the Op-code bits generated by the
instruction register and interprets the operation and addressing
modes of the instruction. Now, based on operation and addressing
mode of the instruction in instruction register it set the
corresponding Instruction signal INSi to 1.
 Each instruction is executed in step-like, instruction fetch, decode,
operand fetch, ALU, memory store. These steps may vary in
different books. But in general, five steps are enough to for the
execution of an instruction.

Mr. Sagar Pandya
 Now, the control unit must be aware of the current step, the
instruction is in.
 For this, a Step Counter is implemented which has signals from T1,
…, T5.
 The step counter sets one of the signals T1 to T5 to 1 on the basis of
the step, the instruction is in.
 Here, the question arises how step counter knows the current step of
the instruction? For this, a Clock is implemented.
 This clock is designed such that for each step the clock must
complete its one clock cycle.
 So, consider if the step counter has set T3 signal 1 then after a clock
cycle completes step counter will set T4 to 1.

Mr. Sagar Pandya
 What if the execution of instruction has is interrupted due to some
reason?
 Will the clock still continue to trigger step counter?
 The answer is No.
 The Counter Enable ‘disables’ the step counter to increment to the
next step signal, till the execution of the current step is completed.
 Now, suppose the execution of an instruction depends on some
condition or if it is branch instruction.
 This is determined with the help of the Condition signals.
 The Condition signals generate the signals for the conditions greater
than, less than, equal, greater than equal, less than equal etc.

Mr. Sagar Pandya
 The remaining is External inputs, it acknowledges the control signal
generator of interrupts which affects the execution of the instruction.
 On an, all the Control Signal Generator generates the control signals,
based on the inputs obtained by the Instruction register, Step
counter, Condition signals and External inputs.
 This organization can be very complicated if we have to make the
control unit large.
 If the design has to be modified or changed, all the combinational
circuits have to be modified which is a very difficult task.

Mr. Sagar Pandya

Microprogrammed Control Unit
Mr. Sagar Pandya
 What is Microprogrammed Control Unit?
 Microprogrammed control unit also produces the control signal but
using the programs.
 This approach was very popular in past during the evolution of
CISC architecture.
 The program that creates the ‘control signals’ is called
Microprogram.
 This microprogram is placed on the processor chip which is fast
memory, it is also called control memory or control store.
 A microprogram has a set of microinstructions, or it is also termed
as control word.
 Each microinstruction is ‘n’ bit word.

Mr. Sagar Pandya
 Each control signal differs from other control signal depending on
the bit pattern of the control word.
 Each control word/microinstruction has a different bit pattern.
 A sequence of microinstructions required to execute a particular
instruction is called micro routine.
 The Control memory address register specifies the address of the
micro-instruction.
 The Control memory is assumed to be a ROM, within which all
control information is permanently stored.
 The control register holds the microinstruction fetched from the
memory.
 The micro-instruction contains a control word that specifies one or
more micro-operations for the data processor.

Mr. Sagar Pandya
 While the micro-operations are being executed, the next address is
computed in the next address generator circuit and then transferred
into the control address register to read the next microinstruction.
 The next address generator is often referred to as a micro-program
sequencer, as it determines the address sequence that is read from
control memory.

Mr. Sagar Pandya
1. Control Word : A control word is a word whose individual bits
represent various control signals.
2. Micro-routine : A sequence of control words corresponding to the
control sequence of a machine instruction constitutes the micro-
routine for that instruction.
3. Micro-instruction : Individual control words in this micro-routine
are referred to as microinstructions.
4. Micro-program : A sequence of micro-instructions is called a
micro-program, which is stored in a ROM or RAM called a
Control Memory (CM).
5. Control Store : The micro-routines for all instructions in the
instruction set of a computer are stored in a special memory called
the Control Store.

Mr. Sagar Pandya

Mr. Sagar Pandya
 In the first step (instruction fetch) the Microinstruction address
generator would fetch the instruction from ‘instruction register’ (IR).
 In the second step, the microinstruction address generator decodes the
instruction obtained from IR and retrieves the starting address of the
micro-routine required to perform the corresponding operation
mentioned in the instruction. It loads that starting address to
microprogram counter.
 In the third step, the ‘control word’ corresponding to the ‘starting
address’ of ‘microprogram counter’ is read and as the execution
proceeds, microprogram address generator will increment the value of
microprogram counter to read the successive control words of the
micro-routine.

Mr. Sagar Pandya
 In the last microinstruction of a micro-routine, there is a bit which we
call end bit. When end bit is set to 1 it denotes successful execution of
that micro-routine.
 After this, the microprogram address generator would return back to
Step 1 again to fetch a new instruction. And the cycle goes on.
 Control Store or Control memory is a memory used store the
microprograms.
 A microprogram control unit is simple to implement and flexible to
modify but it is slower than Hardwired control unit.
 Similarities:
 Both Hardwired and Microprogrammed control unit ‘generates’ the
control signals.

Hardwired vs Microprogrammed Control Unit
Mr. Sagar Pandya
Hardwired Control Microprogrammed Control
Technology is circuit based. Technology is software based.
It is implemented through flip-
flops, gates, decoders etc.
Microinstructions generate signals
to control the execution of
instructions.
Fixed instruction format.
Variable instruction format (16-64
bits per instruction).
Instructions are register based. Instructions are not register based.

Hardwired vs Microprogrammed Control Unit
Mr. Sagar Pandya
Hardwired Control Microprogrammed Control
No control memory is required Control memory is required
It is used in RISC. It is used in CISC.
Faster decoding. Comparatively slow
Difficult to modify. Easily modified.
Chip area is less. Chip area is large.

Unit – 2
Assignment Questions Marks:-20
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 Q.1 What do you mean by addressing mode? Explain following types
of addressing modes with example.
i. Indexed mode ii. Register indirect mode
iii. Relative mode iv. Auto Decrement mode
 Q. 2 How the CPU has organized with Stack implementation?
Specify the operation of Stack organization.
 Q.3 Distinguish between RISC and CISC.
 Q.4 What is the function of control unit? Differentiate hardwired and
microprogrammed control unit.
 Q.5 Explain Block diagram of ALU. Discuss about multiple bus
organization data path.

Thank You
Great God, Medi-Caps, All the attendees
Mr. Sagar Pandya
www.sagarpandya.tk
LinkedIn: /in/seapandya
Twitter: @seapandya
Facebook: /seapandya

UNIT-2.pptx

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