Register transfer language, hardware implementation of bus transfer using multiplexer and three state buffer, hardware implementation of memory transfer e.g., memory read and memory write.

1. REGISTER TRANSFER
AND
MICROOPERATIONS
PART 1
Dr. Prasenjit Dey

2. Contents
DR. PRASENJIT DEY 2
 What is Register Transfer Language
 How Register Transfer happens
 How Bus transfer is implemented
 How Memory transfer is implemented

3. Introduction
Digital Module
 Consists of a set of registers and a set of instructions/operations
 Instructions are performed on the data stored in the registers
Digital System
 Digital modules interconnected with various data and control buses
to perform certain tasks on the data forms a digital system
DR. PRASENJIT DEY 3

4. Introduction cont.
The hardwires of a digital computer are:
1. The set of registers that contains the data
2. The sequence of microoperations that perform on the binary
information stored in the registers
3. The control unit that initiates the sequence of microoperations
Digital System = Registers + Microoperations + Control circuit
DR. PRASENJIT DEY 4

5. Introduction cont.
Micro-instructions/Micro-operations
 Instructions executed on the binary data stored in the registers
 Any digital computer operation consists of a set of micro-instructions
also called micro-operations
Example
 1-bit left shift the content of a register R
 SHL R,1 (R << 1)
DR. PRASENJIT DEY 5
101101110011 1011011100110
1-bit Left Shift Operation

6. Register Transfer Language (RTL)
Register Transfer Language (RTL)
 A symbolic notation to describe the sequence of microoperations which are
used to manipulate or transfer data from a register to another register
 LW R1,M[x04] [load the content of memory location (x04) into register R1 ]
Computer registers are denoted by capital letters sometimes followed
by numerals, e.g.,
 R1: Register 1 (In MIPS there are 32 registers)
 MAR: Memory Address Register (holds a memory address location)
 PC: Program Counter (holds memory address of the next executable instruction)
 IR: Instruction Register (holds the instruction which is going to be executed)
 SR: Status Register (holds the status information of an operation)
DR. PRASENJIT DEY 6

7. Register Denotations
A computer register consists of a set of flip-flops
 An n-bit register contains n flip-flops (FFs), each capable of storing 1 bit of
information
 The FFs are numbered from right to left, the left most FF contains the most
significant bit (MSB) and right most FF contains the least significant bit
(LSB)
 A register can be represented in the following manners
DR. PRASENJIT DEY 7
R1 7 6 5 4 3 2 1 0
Register R1 Showing individual bits
MSB LSB
PC
Numbering of bits
15 0
Partitioned into two parts
PC(H) PC(L)
07815
Lower byteUpper byte

8. Register Transfer
R2 ← R1
It denotes a transfer of the content from register R1 into register R2
The transfer of all bits happens in one clock cycle. Data lines should
exist between R1 and R2 for parallel loading n-bits
The content of the R1 (source) does not change
The content of the R2 (destination) will overwritten by the content of
R1
DR. PRASENJIT DEY 8

9. Conditional Register Transfer
Conditional transfer occurs only under a control condition
Representation of a (conditional) transfer
P: R2 ← R1
Here a control signal p (P equals to 0 or 1) determines when the
transfer occurs
The content of R1 is transferred into R2 only if P is 1
DR. PRASENJIT DEY 9

10. Hardware implementation
DR. PRASENJIT DEY 10
n
Clock
R1
R2
Control
Circuit
Load
t t+1
Clock
Load
Transfer when positive edge triggered
Synchronized
with the clock
PBlock diagram:
Timing diagram

11. Register Transfer Representations
Basic Symbols for Register Transfers
Symbol Description Examples
Letters &
numerals
Denotes a register MAR, R2
Parenthesis ( ) Denotes a part of a
register
R2(0-4), R2(L)
Arrow ← Denotes transfer of
information
R2 ← R1
Comma , Separates two
microoperations
R2 ← R1, R1 ←
R2
DR. PRASENJIT DEY 11

12. Bus Transfer
DR. PRASENJIT DEY 12
A digital computer has many registers
If there exists a data and control paths between every pair to registers
then
 there will be nc2=n(n-1) paths for n registers and the complexity will be O(n2)
The Bus System
 A set of common lines, one for each bit of a register, through which binary
information is transferred one at a time is called bus
 A centralized bus, all registers are connected with a single data bus for data
transfer
 Control bus determines which register is selected as a source and which
register is selected as destination during each particular register transfer
R1 R3
Data Bus
R2
R(n-1)
R4 Rn

13. Hardware implementation: Multiplexer
DR. PRASENJIT DEY 13
3 2 1 0
Register D
D3 D2 D1 D0
3 2 1 0
Register C
C3 C2 C1 C0
3 2 1 0
Register B
B3 B2 B1 B0
3 2 1 0
Register A
A3 A2 A1 A0
D3 C3 B3 A3
S0
S1
MUX3
3 2 1 0
D2 C2 B2 A2
S0
S1
MUX2
3 2 1 0
D1 C1 B1 A1
S0
S1
MUX1
3 2 1 0
D0 C0 B0 A0
S0
S1
MUX0
3 2 1 0
4-Line Common Bus
Register A Register B Register C Register D
Bus lines
S0=0
S1=0
Input(n)
Selection
line (log2n)MUX
Output(1)

14. Question & Answer
Q1: How many selection lines are required to select a register among m
registers?
A: 𝑙𝑜𝑔2(𝑚)
Q2: How many multiplexers are needed if their exists n bits in each
register?
A: n
DR. PRASENJIT DEY 14

15. Bus Transfer cont.
The transfer of information from a bus into one of many
destination registers is done:
1. By connecting the bus lines to the inputs of all destination
registers and then:
2. activating the load control of the particular destination register
selected
R1 ← B
symbolize that the content of register B is loaded into the
register R1 using the common system bus
It is equivalent to: BUS ←B, (select B)
R1 ←BUS (Load R1)
DR. PRASENJIT DEY 15

16. Three State Bus Buffers
Three-state buffer gates are alternative of multiplexers for
implementing a bus system
A three-state buffer is a digital circuit that exhibits three states:
◦ logic-0, logic-1, and high-impedance (Hi-Z)
DR. PRASENJIT DEY 16
Normal input A
Control input C
Three-State Buffer
Output B

17. Three State Bus Buffers cont.
DR. PRASENJIT DEY 17
A
C=1
B A B
A
C=0
B A B
Buffer
Open Circuit

18. Hardware implementation: Three-State Bus
Buffers
DR. PRASENJIT DEY 18
2×4
Decoder
Select
Enable
0
1
2
3
S1
S0
E
Bus line for bit 1
A1
B1
C1
D1

19. Memory Transfer
Transfer from memory Memory read
Transfer to memory Memory write
The data content in the memory operation is called memory word (M)
A memory word is denoted by letter M followed by enclosing the
memory address in square brackets
 Example: M[ox0016] : the memory contents at address ox0016
DR. PRASENJIT DEY 19
data input lines
data output lines
n
n
k
address lines
Read
Write
Memory
unit

20. Memory Transfer cont.
The address of a memory unit is stored in a register called Memory Address
Register(MAR)
The data stored in a register called Data Register(DR)
 Read: DR ← M[MAR] Write: M[MAR] ← DR
Let, read the data from memory word ‘0x10’ into register R1
DR. PRASENJIT DEY 20
MAR
0x10
0x04
0x08
0x0C
0x10
0x14
23
36
17
61
99
R1←M[MAR]
R1
22
Memory
R1
2261