vlsi,plds cpld,fpga,spld,pal,pla

1. NAME - OMPRAKASH SAHU
ROLL NO. – 301602818312
BRANCH – ET&T 6TH SEM.
SUBJECT – VLSI DESIGN
Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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2. 6
Cutaway view of one type of fixed-function IC package showing the chip mounted inside, with
connection to input an output pins.
FIXED-FUNCTION INTEGRATED
CIRCUITS
2/7/2020Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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3. INTRODUCTIO
N
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• In fixed function devices a specific logic
function is contained in the IC package when it
is purchased and it can never be changed.
• Another category of logic device is one in
which the logic function is programmed by
user and, in some cases, can be
reprogrammed many times.
• These devices are called programmable logic
devices or PLDs.

4. INTRODUCTION PLDS
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Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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• Programmable logic devices (PLD) refers to integrated circuits
which can be programmed to implement any digital system.
PLDs were introduced in 1970s with the idea to design a
single purpose chip which can be programmed to meet
particular hardware requirements.
• PLDs are semiconductor devices that can be programmed to
obtain required logic device. Because of the advantage of re-
programmability, they have replaced special purpose logic
devices like Logic gates, flip-flops, counters and multiplexers
in many semicustom applications. It reduces design time and
thus reduces time for the product to reach the market. It
consists of arrays of AND and OR gates, which can be
programmed to realize required logic function.

5. BASI
C
IDE
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6. Advantages of using PLDs
- Advantages of using PLDs are less board
space, faster
- lower power requirements (i.e., smaller
power supplies)
- less costly assembly processes, higher
reliability (fewer ICs and circuit connections
means easier troubleshooting)
- availability of design software.
2/7/2020Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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7. TYPE OF PLDS
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• The three major types of programmable logic
are :-
1) SPLD (Simple Programmable Logic devices)
2) CPLD (Complex Programmable Logic Devices)
and
3) FPGA (Field Programmable Gate Array).

8. SPLDS
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• The least complex form of PLDs.
• Can typically replaced several fixed function SSI
or MSI devices and their connections.
• A typical package has 24 to 28 pins.
• A few categories of SPLD are listed below:-
- PAL (Programmable Array Logic)
- GAL (Generic Array Logic)
- PLA (Programmable Logic Array)
- PROM (Programmable Read-Only Memory)

9. SPLD
 SPLD ATF16V8B Family IC
2/7/2020Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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10. CPLDS
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• Much higher capacity than SPLDs, permitting
more complex logic circuits to be programmed
into them.
• A typical CPLD is the equivalent of from 2 to
64 SPLDs and come in 44 pins to 160 pin
packages depending on the complexity.
• There are several forms of CPLD, which vary in
complexity and programming capability.

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Typical CPLD packages.
CPLDs are made using 2 to 64 SPLDs
2/7/2020Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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12. FAMILIES-OF-CPLD
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13. 20
GENERALIZED PLD
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A generic PLD for implementing SOP functions has:
Inverter/buffer
array for inputs
AND array OR array

14. PROGRAMMABLE LOGIC
DEVICES (PLDS)
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Programmable
AND array
Fixed
ORarrayconnections OutputsInputs
Programmable
Programmable array logic (PAL) device
Programmable
AND array
Programmable
OR arrayconnections OutputsInputs
Programmable Programmable
connections
All use AND-OR structure- differ in which is programmable
Programmable logic array (PLA)

15. PROGRAMMABLE LOGIC ARRAY (PLA)
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• A programmable logic array (PLA) is a kind of programmable logic
device used to implement combinational logic circuits. The PLA has a
set of programmable AND gate planes, which link to a set of
programmable OR gate planes, which can then be conditionally
complemented to produce an output.
• AND array and OR array
are programmable
• XOR is available to complement
an output if needed
• Example:
• 3 inputs/2 outputs
• F1 = A B’ + A C + A’ BC’
• F2 = (AC + BC)’

16.  BLOCK DIAGRAM
 Programmable logic array
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Programmable
AND array
Programmable
OR arrayconnections OutputsInputs
Programmable Programmable
connections
Programmable logic array (PLA)

17. PLA/GAL
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18. PROGRAMMABLE ARRAY LOGIC (PAL)
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• Programmable Array Logic (PAL) is a family of programmable logic
device semiconductors used to implement logic functions in digital
circuits introduced by Monolithic Memories, Inc MMI obtained a
registered trademark on the term PAL for use in "Programmable
Semiconductor Logic Circuits".
• Fixed OR array and
programmable AND array
• Opposite of ROM!
• Example:
• 4 inputs/4 outputs with
fixed 3- input OR gates
• W = A B C’ + A’ B’ C D’

19.  BLOCK DIAGRAM
 Programmable Array Logic
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Programmable
AND array
Fixed
ORarrayconnections OutputsInputs
Programmable
Programmable array logic (PAL) device

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PAL
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CE16V3H-25 IC.

21. FPGA
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Introduction:- The full form of FPGA is “Field Programmable Gate
Array”. It contains ten thousand to more than a million logic gates
with programmable interconnection. Programmable interconnections
are available for users or designers to perform given functions easily.
• Have the greatest logic capacity.
• Consist of an array of anywhere from 64 to thousands of logic
gates groups that are sometimes called logic blocks.
• Two basics classes of FPGA are course grained
and fine grained.
• FPGAs come in packages ranging up to 1000 pins or more.

22. FIELD PROGRAMMABLE GATE
ARRAY (FPGA)
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• Xilinx FPGAs
• Configurable Logic Block
(CLB)
• Programmable logic
and FFs
• Programmable
Interconnects
• Switch Matrices
• Horizontal/vertical
lines
• I/O Block (IOB)
• Programmable I/O pins

23. FIELD PROGRAMMABLE GATE
ARRAYS
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– a programmable device using more complex cells

24. FPGA IC
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25. SPECIAL FPGA FUNCTIONS
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• Internal SRAM
• Embedded Multipliers
and DSP blocks
• Embedded logic analyzer
• Embedded CPUs
• High speed I/O (~10GHz)
• DDR/DDRII/DDRIII SDRAM
interfaces
• PLLs

26. 17
PLD programmer – this piece of hardware might
contain a universal socket that could hold various
types of PLD’s. The PLD software produces a JEDEC
file which is downloaded into the programmer. The
programmer can typically program, copy,
Computer with PLD
programming software
JEDEC file
downloaded
PLD Programmer
PLD inserted
into socket
2/7/2020Omprakash sahu /ET&T/ 6th sem / GEC Raipur.
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