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Efficiency Evaluation of Single-Phase Solutions for
AC-DC PFC Boost Converters for Plug-in-Hybrid
Electric Vehicule Battery Chargers
Fariborz Musavi
Delta-Q Technologies Corp.
Unit 3, 5250 Grimmer Street
Burnaby, BC, Canada
fmusavi@delta-q.com

Abstract— In this paper, the bridgeless interleaved boost topology
is proposed for plug-in hybrid electric vehicle and electric vehicle
battery chargers to achieve high efficiency, which is critical to
minimize the charger size, charging time and the amount and
cost of electricity drawn from the utility. An analytical model for
this topology is developed, enabling the calculation of power
losses and efficiency. Experimental and simulation results of
prototype units converting the universal AC input voltage to 400
V DC at 3.4 kW are given to verify the proof of concept, and
analytical work reported in this paper.
Keywords-component; Boost Converter; Single phase PFC;
Interleaved PFC; Bridgeless PFC; PHEV Charger;

I.

Wilson Eberle and 2 Wiliam G. Dunford

Department of Electrical and Computer Engineering
University of British Columbia | 1 Okanagan | 2 Vancouver
1
Kelowna, BC, Canada | 2 Vancouver, BC, Canada
1
wilson.eberle@ubc.ca | 2 wgd@ece.ubc.ca
followed by the boost section, as shown in Figure 1. In this
topology, the output capacitor ripple current is very high [6, 7]
and is the difference between diode current and the dc output
current. Furthermore, as the power level increases, the diode
bridge losses significantly degrade the efficiency, so dealing
with the heat dissipation in a limited area becomes problematic.
Due to these constraints, this topology is good for a low to
medium power range up to approximately 1kW. For power
levels >1kW, typically, designers parallel semiconductors in
order to deliver greater output power. The inductor volume also
becomes a problematic design issue at high power.
LB

INTRODUCTION

A plug-in hybrid electric vehicle (PHEV) is a hybrid
vehicle with a storage system that can be recharged by
connecting the vehicle plug to an external electric power
source. In recent years, PHEV motor drive and energy storage
technology has developed at a rapid rate in response to
expected market demand for PHEVs. Battery chargers are
another key component required for the emergence and
acceptance of PHEVs. For PHEV applications, the accepted
approach involves using an in-vehicle charger [1]. An invehicle 3.4 kW charger can charge a depleted battery pack in
PHEVs to 95% charge in about four hours from a 240 V
supply [2]. The accepted charger power architecture includes
an AC-DC converter with power factor correction (PFC) [3]
followed by an isolated DC-DC converter. Selecting the
optimal topology and evaluating power losses in power
semiconductors are important steps in the design and
development of these battery chargers [4]. The front-end ACDC converter is a key component of the charger system. In the
following sub-sections, three common continuous conduction
mode (CCM) AC-DC PFC boost converters are evaluated.
II.

1

D1

DB

D4

Vin
QB
D2

Co

L
O
A
D

D3

Figure 1: Conventional PFC boost converter

B. Bridgeless Boost Converter
The bridgeless boost converter topology [8-12] avoids the
need for the rectifier input bridge, yet maintains the classic
boost topology, as shown in Figure 2. It is an attractive solution
for applications >1kW, where power density and efficiency are
important. The bridgeless boost converter solves the problem
of heat management in the input rectifier diode bridge, but it
introduces increased EMI [13, 14].

REVIEW OF EXISTING TOPOLOGIES

A. Conventional Boost Converter
The conventional boost topology is the most popular
topology for PFC applications [5]. It uses a dedicated diode
bridge to rectify the AC input voltage to DC, which is then
Figure 2: Bridgeless PFC boost topology
Another disadvantage of this topology is the floating input line
with respect to the PFC stage ground, which makes it
impossible to sense the input voltage without a low frequency
transformer or an optical coupler. Also in order to sense the
input current, complex circuitry is needed to sense the current
in the MOSFET and diode paths separately, since the current
path does not share the same ground during each half-line
cycle [9, 15].
C. Interleaved Boost Converter
The interleaved boost converter, Figure 3, is simply two
boost converters in parallel operating 180° out of phase [1618]. The input current is the sum of the two inductor currents
ILB1 and ILB2. Because the inductors’ ripple currents are out of
phase, they tend to cancel each other and reduce the input
ripple current caused by the boost switching action. The
interleaved boost converter has the advantage of paralleled
semiconductors. Furthermore, by switching 180° out of phase,
it doubles the effective switching frequency and introduces
smaller input current ripples, so the input EMI filters will be
smaller [19, 20]. It also reduces output capacitor high
frequency ripple [21]. But it still has the problem of heat
management for the input diode bridge rectifiers.

the Load and returns through the body diode of Q2 back to the
mains.
The same cycle happens for Q3, but with a 180° phase
delay. During the “negative” half cycle, Q2 and Q4 turn on,
current flows through the inductors L2 and L1 (L4 and L3 for
the interleaved one). When the MOSFETs are off, energy is
released as current flows through D2 (and D4), through load
and back to the main through the body diode of Q1 (and Q3). A
detailed converter description is given in [22].
IV.

ANALYTICAL MODELLING

In order to properly select the power stage components of a
converter and calculate the associated power losses, it is
necessary to determine the RMS and average values of their
currents. In a typical boost converter, the FET and diode
current waveforms are pulsed-width modulated, with both the
duty cycle and peak amplitude varying with the AC input. And
without an effective mathematical method for computing these
RMS and average values, the proper design and selection of
power stage components can be flawed. The following
assumptions were made in order to analyze the converters and
to derive the stress equations:
a) These calculations are based on the operation of CCM
PFC boost converter.
b) Assuming unity power factor, the line current is in phase
and shape with the input line voltage – a sinusoidal
waveform.
c) The PFC output voltage is DC with no voltage ripple.
In a typical boost converter, the converter FET duty cycle is
given by:
1

|

|

1

|

|

(1)

Figure 3: Interleaved PFC boost topology

III.

BRIDGELESS INTERLEAVED BOOST TOPOLOGY

The BLIL PFC shown in Figure 4 is proposed as a solution
to problems addressed. Compared to the interleaved PFC
converter, this topology introduces two more FETs and two
more fast diodes in place of 4 slow diodes used in input bridge.

Assuming the inductor current is a sinusoidal waveform:
(2)

|sin θ |

The instantaneous FET current and its RMS current can be
derived respectively:
|

|sin θ | 1
|

|sin θ | 1

|

|

(3)
(4)

The inducotr current ripple is assumed to be half of peak
inductor current:
(5)

∆
Figure 4: Bridgeless Interleaved PFC boost topology

To analyze the circuit operation, it has been separated into
two half cycles. During the “positive” half cycle, when AC
input voltage goes positive, Q1 turns on and current flows
through L1, Q1 and continues through Q2 and then L2 to store
energy in L1 and L2. When Q1 turns off, energy stored in L1
and L2 will be released as current flows through D1, through

The high frequency ripple components of inductor current is
assumed to be a triangler waveform with a fixed duty cycle, so
the RMS current in each inductor is defined by:

√

√

∆

√

(6)
TABLE I.

SUMMARY OF COMPONENT RMS CURRENT STRESS FOR CONVENTIONAL BOOST AND BRIDGELESS BOOST TOPOLOGIES

Topology

Conventional PFC
97
48

Boost Inductor 

Bridgeless PFC
97
48

 

Not Applicable

Input Bridge Diode

√3
2

3
2

Boost Fast Diode
3

Boost Transistor

3

4

64

√6

3

3

4

64

√6
√3
2

Not Applicable

Boost Transistor Intrinsic Diode

√2
2

Output Capacitor Ripple (LF) 
√2
2

Output Capacitor Ripple (HF) 

TABLE II.

 

√2
2

 

3

2

√2
2

 

 

3

2

 

SUMMARY OF COMPONENT CURRENT STRESS FOR INTERLEAVED AND BRIDGELESS INTERLEAVED BOOST TOPOLOGIES

Topology

Interleaved PFC
5

Boost Inductor 

Bridgeless Interleaved PFC
5

 

4√3

 

4√3

Not Applicable

Input Bridge Diode

√3
4

3
2 2.

Boost Fast Diode
3

Boost Transistor

3

4

64

2√6

√2
2

Output Capacitor Ripple (LF) 

16
6

Output Capacitor Ripple (HF) 

|

|

1.5

(7)

Therefore the instantaneous boost diode current and its RMS
current can be derived respectively:

|sin θ |

|

|

|

4

√2
2

 

The boost diode duty cycle is given by:

|sin θ |

3

64

√3
4

Not Applicable

Boost Transistor Intrinsic Diode

1

3
2√6

(8)
|

 

16
6

 

1.5

The output capacitor current has high frequency and low
frequency components. The low frequency component is
simply calculated by:
√
√

(10)

And the high frequency RMS ripple current component is:
1.5

(9)

 

(11)

The same method was used to derive RMS current in
different topologies. Table 1 shows a summary of component
Bridgeless Boost

8.1W

0.0W

0.0W

8.1W

21.6W
6.9W
9.8W
6.9W
9.7W

0W

0.0W

10

5.4W
10.8W

30
20

28.7W

Bridgeless Interleaved Boost

10.8W

30.0W

30.0W

Interleaved Boost
40

Device / Total Losses 

25

Total Losses

Intrinsic
Body Diodes

FETs

Fast Diodes

0
Regular
Diodes

Also the low frequency RMS ripple current through output
capacitors is constant and interleaving has no effect on it. But
the high frequency ripple current will be reduced significantly,
as it is shown in Figure 5. Also it is noted that as the input
voltage increases, the high frequency ripple reduces.

Conventional Boost

50

Power  Losses (W)

As can be noted, in both the bridgeless topology and
bridgeless interleaved topology, a new loss has been introduced
in the intrinsic body diodes of the FETs, but since input bridge
rectifiers were eliminated, there is some efficiency gain in
overall performance of these topologies. The intrinsic body
diode of FETs conduct when the boost transistors are off and
its value is the same as the current in the boost diodes, when
they conduct and transfer energy to the output capacitors.

60

47.7W
39.4W
42.3W

RMS current stress for conventional boost converter and
bridgeless boost converter. Table 2 provides the same summary
for interleaved boost converter and bridgeless interleaved boost
converter.

Figure 6: Loss distribution in semiconductors
High Frequency
Capacitor Ripple
Current in
Conventional PFC

18.75
High Frequency
Capacitor Ripple
Current in IL PFC

VI.

EXPERIMENTAL RESULTS

A prototype of the bridgeless interleaved converter circuit
was built to verify proof-of-concept and analytical work
presented in this paper as shown in Figure 7. The performance
was compared with a benchmark interleaved boost converter.

Ripple
12.5
(A)

6.25
Low Frequency
Capacitor
Ripple Current
0

0

75

150

225

300

Vin (V)

Figure 5: RMS ripple current through output capacitors vs input voltage

V.

LOSS EVALUATION

Figure 6 shows the loss distribution of the semiconductors
in the four topologies investigated in this paper. The regular
diodes in input bridge rectifiers have the largest share of losses
among the topologies with the input bridge rectifier. The
bridgeless topologies eliminate this large loss component
(~30W). However, the tradeoff is that the FET losses are higher
and the intrinsic body diodes of FETs conduct, producing new
losses (~8W).
The fast diodes in the conventional and
interleaved PFC have slightly lower power losses, since the
boost RMS current is higher in these topologies. Overall the
FETs are under more stress in bridgeless topologies, but the
total loss for the proposed bridgeless interleaved boost are 40%
lower than the benchmark conventional boost, 27% lower than
the bridgeless boost and 32% lower than the interleaved boost .
Since the bridge rectifier losses are so large, it was expected
that bridgeless interleaved boost converter would have the least
power losses among all four introduced topologies. Also it was
noted that the losses in the input bridge rectifiers were 63% of
total losses in conventional PFC converter and 71% of total
losses in interleaved PFC converter. Therefore eliminating the
input bridges in PFC converters is justified despite the fact that
new losses are introduced.

Figure 7: Breadboard prototype of BLIL PFC

Table 3 shows the semiconductors and power components
used in the 3.4 kW CCM experimental prototypes – an
interleaved boost PFC converter and a bridgeless interleaved
PFC converter. The prototypes were built for a universal acline input (85~265 V) RMS at 400 V output.
Figures 8 to 11 show the converter efficiency versus output
power for interleaved boost PFC converter and bridgeless
interleaved boost PFC converter at different input voltages and
the following test conditions: fsw = 70 kHz, Iin = 15 A and Vo =
400 V. Since the input current is kept constant at 15 A, the
output power is varying from 1200 W for 90 V input, 1.7 kW
for 120 V input, 3 kW for 220 V input and 3.4 kW for 240 V
input voltage. As it can be seen, for interleaved PFC the
maximum efficiency of 97.5% is reached at 240 V input and
around 2 kW output power. But as the input voltage reduces,
TABLE III.

DEVICES/COMPONENTS USED IN PROTOTYPE UNITS
Device

Part # / Value

# of
devices

98
97
96

Interleaved PFC Converter

95

Bridgeless Interleaved PFC
Converter

Fast Diode

IDB06S60C

2

MOSFET

IPB60R099CP

2

Inductor

800 μH

2

Fast Diode

CSD10060

4

MOSFET

IPP60R099CP

4

Inductor

400 μH

4

94

3000

2500

2000

1500

1000

500

0

93

PFC

Bridgeless

99

4

Interleaved PFC

25ETS08S

Regular Diode

Interleaved

Topology

100

Efficiency (%)

the overall efficiency drops significantly as expected, where it
is around 94.5% for 90 V input. Also it is noticed that at
lighter loads, especially for low input lines, converter
efficiency drops as low as 91% for 100 W and 90 V input.

Output Power (W)
Figure 9: Efficiency vs. output power for Interleaved and Bridgeless
Interleaved PFC Boost Converter at Vin = 220 V

100
99
98

Efficiency (%)

100

98

96
95
94

Interleaved PFC
Converter
Bridgeless Interleaved
PFC Converter

93

97
Interleaved PFC
Converter

92

1800

1600

1400

1200

1000

800

600

95

400

91

Bridgeless Interleaved
PFC Converter

200

96

0

Efficiency (%)

99

97

Output Power (W)

100

96
95
94
93
92
91
1200

1000

800

90
600

A Yokogawa W230 digital power meter was used for
efficiency measurements. A Chroma 63202 DC electronic load
and an Agilent 6834B AC source/Analyzer were also used in
the experiments.

Bridgeless Interleaved
PFC Converter

97

0

For bridgeless interleaved PFC, the overall efficiency drops
at lower input voltages as expected, where it is around 96% for
90 V input.

98

Efficiency (%)

But a higher maximum efficiency of 98.5% was reached at
240 V input and around 2 kW output power for bridgeless
interleaved PFC converter. Also it is noticed that at lighter
loads, especially for low input lines, converter efficiency is
improved significantly (as high as 3% at 200 W) compared to
interleaved boost converter.

Interleaved PFC
Converter

99

Figure 8: Efficiency vs. output power for Interleaved and Bridgeless
Interleaved PFC Boost Converter at Vin = 240 V

400

Output Power (W)

Figure 10: Efficiency vs. output power for Interleaved and Bridgeless
Interleaved PFC Boost Converter at Vin = 120 V

200

3500

3000

2500

2000

1500

1000

500

0

94

Output Power (W)
Figure 11: Efficiency vs. output power for Interleaved and Bridgeless
Interleaved PFC Boost Converter at Vin = 90 V
VII. CONCLUSION
A new high efficiency bridgeless interleaved PFC AC-DC
Boost converter topology has been presented in this paper. The
target application for the converter is the front-end AC-DC
converter in plug-in hybrid electric vehicle battery chargers.
The proposed converter has been analyzed and its performance
characteristics have presented. Also an analytical model for
four different topologies was developed, enabling the
calculation of power losses and efficiency calculation. A
breadboard converter circuit has been built to verify the proofof-concept. The proposed converter shows a high efficiency
(~98.5 %), especially for lighter loads and lower input voltages,
high input power factor and excellent input current harmonics.

REFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]
[9]

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Lisheng Shi; Meintz, A.; Ferdowsi, M., "Single-Phase Bidirectional ACDC Converters for Plug-in Hybrid Electric Vehicle Applications," IEEE
Vehicle Power and Propulsion Conference, VPPC, pp. 1 - 5 2008.
Singh, B.; Singh, B.N.; Chandra, A.; Al-Haddad, K.; Pandey, A.;
Kothari, D.P., "A Review of Single-Phase Improved Power Quality ACDC Converters," IEEE Transactions on Industrial Electronics, vol. 50,
pp. 962 - 981, 2003.
Jinjun Liu; Weiyun Chen; Jindong Zhang; Dehong Xu; Lee, F.C.,
"Evaluation of power losses in different CCM mode single-phase boost
PFC converters via a simulation tool " in IEEE Industry Applications
Conference. vol. 4, 2001, pp. 2455 - 2459.
Liyu Yang; Bing Lu; Wei Dong; Zhiguo Lu; Ming Xu; Lee, F.C.;
Odendaal, W.G., "Modeling and Characterization of a 1KW CCM PFC
Converter for Conducted EMI Prediction," in IEEE Applied Power
Electronics Conference and Exposition, APEC. vol. 2, 2004, pp. 763 769.
C. L. Sirio, "Analysis of Line Current Harmonics for Single-Phase PFC
Converters," in IEEE Power Electronics Specialists Conference, 2007,
pp. 1291 – 1297.
Dehong Xu; Jindong Zhang; Weiyun Chen; Jinjun Lin; Lee, F.C.,
"Evaluation of output filter capacitor current ripples in single phase PFC
converters " in Proceedings of the Power Conversion Conference, PCC.
vol. 3 Osaka, Japan, 2002, pp. 1226 - 1231.
D. Mitchell, "AC – DC converter having an improved power factor,"
United States Patent # 4412277, 1983.
U. Moriconi, "A Bridgeless PFC Configuration based on L4981 PFC
Controller ": STMicroelectronics Application Note AN1606, 2002.

[10] Woo-Young Choi; Jung-Min Kwon; Eung-Ho Kim; Jong-Jae Lee;
Bong-Hwan Kwon, "Bridgeless Boost Rectifier With Low Conduction
Losses and Reduced Diode Reverse-Recovery Problems," IEEE
Transactions on Industrial Electronics, vol. 54, pp. 769 – 780, April
2007 2007.
[11] J. M. Hancock, "Bridgeless PFC Boosts Low-Line Efficiency," Infineon
Technologies, 2008.
[12] Huber, L.; Yungtaek Jang; Jovanovic, M.M., "Performance Evaluation
of Bridgeless PFC Boost Rectifiers," IEEE Transactions on Power
Electronics, vol. 23, pp. 1381 - 1390 2008.
[13] Pengju Kong; Shuo Wang; Lee, F.C., "Common Mode EMI Noise
Suppression for Bridgeless PFC Converters," IEEE Transactions on
Power Electronics, vol. 23, pp. 291 – 297, January 2008 2008.
[14] Baur, T.; Reddig, M.; Schlenk, M., "Line-conducted EMI-behaviour of a
High Efficient PFC-stage without input rectification," Infineon
Technology – Application Note, 2006.
[15] Frank, W.; Reddig, M.; Schlenk, M., "New control methods for rectifierless PFC-stages," in EEE International Symposium on Industrial
Electronics. vol. 2, 2005, pp. 489 - 493
[16] M. O’Loughlin;, "An Interleaved PFC Preregulator for High-Power
Converters." vol. Topic 5: Texas Instrument Power Supply Design
Seminar, 2007, pp. 5-1, 5-14.
[17] Yungtaek Jang; Jovanovic, M.M., "Interleaved Boost Converter With
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End," IEEE Transactions on Power Electronics, vol. 22, pp. 1394 –
1401, July 2007 2007.
[18] Balogh, L.; Redl, R., "Power-factor correction with interleaved boost
converters in continuous-inductor-current mode," in IEEE Applied
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[19] Chuanyun Wang; Ming Xu; Lee, F.C., "Asymmetrical interleaving
strategy for multi-channel PFC," in IEEE Applied Power Electronics
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[20] Pengju Kong; Shuo Wang; Lee, F.C.; Chuanyun Wang, "CommonMode EMI Study and Reduction Technique for the Interleaved
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Efficiency evaluation of single phase solutions for ac-dc pfc boost converters for PHEVs

  • 1. Efficiency Evaluation of Single-Phase Solutions for AC-DC PFC Boost Converters for Plug-in-Hybrid Electric Vehicule Battery Chargers Fariborz Musavi Delta-Q Technologies Corp. Unit 3, 5250 Grimmer Street Burnaby, BC, Canada fmusavi@delta-q.com Abstract— In this paper, the bridgeless interleaved boost topology is proposed for plug-in hybrid electric vehicle and electric vehicle battery chargers to achieve high efficiency, which is critical to minimize the charger size, charging time and the amount and cost of electricity drawn from the utility. An analytical model for this topology is developed, enabling the calculation of power losses and efficiency. Experimental and simulation results of prototype units converting the universal AC input voltage to 400 V DC at 3.4 kW are given to verify the proof of concept, and analytical work reported in this paper. Keywords-component; Boost Converter; Single phase PFC; Interleaved PFC; Bridgeless PFC; PHEV Charger; I. Wilson Eberle and 2 Wiliam G. Dunford Department of Electrical and Computer Engineering University of British Columbia | 1 Okanagan | 2 Vancouver 1 Kelowna, BC, Canada | 2 Vancouver, BC, Canada 1 wilson.eberle@ubc.ca | 2 wgd@ece.ubc.ca followed by the boost section, as shown in Figure 1. In this topology, the output capacitor ripple current is very high [6, 7] and is the difference between diode current and the dc output current. Furthermore, as the power level increases, the diode bridge losses significantly degrade the efficiency, so dealing with the heat dissipation in a limited area becomes problematic. Due to these constraints, this topology is good for a low to medium power range up to approximately 1kW. For power levels >1kW, typically, designers parallel semiconductors in order to deliver greater output power. The inductor volume also becomes a problematic design issue at high power. LB INTRODUCTION A plug-in hybrid electric vehicle (PHEV) is a hybrid vehicle with a storage system that can be recharged by connecting the vehicle plug to an external electric power source. In recent years, PHEV motor drive and energy storage technology has developed at a rapid rate in response to expected market demand for PHEVs. Battery chargers are another key component required for the emergence and acceptance of PHEVs. For PHEV applications, the accepted approach involves using an in-vehicle charger [1]. An invehicle 3.4 kW charger can charge a depleted battery pack in PHEVs to 95% charge in about four hours from a 240 V supply [2]. The accepted charger power architecture includes an AC-DC converter with power factor correction (PFC) [3] followed by an isolated DC-DC converter. Selecting the optimal topology and evaluating power losses in power semiconductors are important steps in the design and development of these battery chargers [4]. The front-end ACDC converter is a key component of the charger system. In the following sub-sections, three common continuous conduction mode (CCM) AC-DC PFC boost converters are evaluated. II. 1 D1 DB D4 Vin QB D2 Co L O A D D3 Figure 1: Conventional PFC boost converter B. Bridgeless Boost Converter The bridgeless boost converter topology [8-12] avoids the need for the rectifier input bridge, yet maintains the classic boost topology, as shown in Figure 2. It is an attractive solution for applications >1kW, where power density and efficiency are important. The bridgeless boost converter solves the problem of heat management in the input rectifier diode bridge, but it introduces increased EMI [13, 14]. REVIEW OF EXISTING TOPOLOGIES A. Conventional Boost Converter The conventional boost topology is the most popular topology for PFC applications [5]. It uses a dedicated diode bridge to rectify the AC input voltage to DC, which is then Figure 2: Bridgeless PFC boost topology
  • 2. Another disadvantage of this topology is the floating input line with respect to the PFC stage ground, which makes it impossible to sense the input voltage without a low frequency transformer or an optical coupler. Also in order to sense the input current, complex circuitry is needed to sense the current in the MOSFET and diode paths separately, since the current path does not share the same ground during each half-line cycle [9, 15]. C. Interleaved Boost Converter The interleaved boost converter, Figure 3, is simply two boost converters in parallel operating 180° out of phase [1618]. The input current is the sum of the two inductor currents ILB1 and ILB2. Because the inductors’ ripple currents are out of phase, they tend to cancel each other and reduce the input ripple current caused by the boost switching action. The interleaved boost converter has the advantage of paralleled semiconductors. Furthermore, by switching 180° out of phase, it doubles the effective switching frequency and introduces smaller input current ripples, so the input EMI filters will be smaller [19, 20]. It also reduces output capacitor high frequency ripple [21]. But it still has the problem of heat management for the input diode bridge rectifiers. the Load and returns through the body diode of Q2 back to the mains. The same cycle happens for Q3, but with a 180° phase delay. During the “negative” half cycle, Q2 and Q4 turn on, current flows through the inductors L2 and L1 (L4 and L3 for the interleaved one). When the MOSFETs are off, energy is released as current flows through D2 (and D4), through load and back to the main through the body diode of Q1 (and Q3). A detailed converter description is given in [22]. IV. ANALYTICAL MODELLING In order to properly select the power stage components of a converter and calculate the associated power losses, it is necessary to determine the RMS and average values of their currents. In a typical boost converter, the FET and diode current waveforms are pulsed-width modulated, with both the duty cycle and peak amplitude varying with the AC input. And without an effective mathematical method for computing these RMS and average values, the proper design and selection of power stage components can be flawed. The following assumptions were made in order to analyze the converters and to derive the stress equations: a) These calculations are based on the operation of CCM PFC boost converter. b) Assuming unity power factor, the line current is in phase and shape with the input line voltage – a sinusoidal waveform. c) The PFC output voltage is DC with no voltage ripple. In a typical boost converter, the converter FET duty cycle is given by: 1 | | 1 | | (1) Figure 3: Interleaved PFC boost topology III. BRIDGELESS INTERLEAVED BOOST TOPOLOGY The BLIL PFC shown in Figure 4 is proposed as a solution to problems addressed. Compared to the interleaved PFC converter, this topology introduces two more FETs and two more fast diodes in place of 4 slow diodes used in input bridge. Assuming the inductor current is a sinusoidal waveform: (2) |sin θ | The instantaneous FET current and its RMS current can be derived respectively: | |sin θ | 1 | |sin θ | 1 | | (3) (4) The inducotr current ripple is assumed to be half of peak inductor current: (5) ∆ Figure 4: Bridgeless Interleaved PFC boost topology To analyze the circuit operation, it has been separated into two half cycles. During the “positive” half cycle, when AC input voltage goes positive, Q1 turns on and current flows through L1, Q1 and continues through Q2 and then L2 to store energy in L1 and L2. When Q1 turns off, energy stored in L1 and L2 will be released as current flows through D1, through The high frequency ripple components of inductor current is assumed to be a triangler waveform with a fixed duty cycle, so the RMS current in each inductor is defined by: √ √ ∆ √ (6)
  • 3. TABLE I. SUMMARY OF COMPONENT RMS CURRENT STRESS FOR CONVENTIONAL BOOST AND BRIDGELESS BOOST TOPOLOGIES Topology Conventional PFC 97 48 Boost Inductor  Bridgeless PFC 97 48   Not Applicable Input Bridge Diode √3 2 3 2 Boost Fast Diode 3 Boost Transistor 3 4 64 √6 3 3 4 64 √6 √3 2 Not Applicable Boost Transistor Intrinsic Diode √2 2 Output Capacitor Ripple (LF)  √2 2 Output Capacitor Ripple (HF)  TABLE II.   √2 2   3 2 √2 2     3 2   SUMMARY OF COMPONENT CURRENT STRESS FOR INTERLEAVED AND BRIDGELESS INTERLEAVED BOOST TOPOLOGIES Topology Interleaved PFC 5 Boost Inductor  Bridgeless Interleaved PFC 5   4√3   4√3 Not Applicable Input Bridge Diode √3 4 3 2 2. Boost Fast Diode 3 Boost Transistor 3 4 64 2√6 √2 2 Output Capacitor Ripple (LF)  16 6 Output Capacitor Ripple (HF)  | | 1.5 (7) Therefore the instantaneous boost diode current and its RMS current can be derived respectively: |sin θ | | | | 4 √2 2   The boost diode duty cycle is given by: |sin θ | 3 64 √3 4 Not Applicable Boost Transistor Intrinsic Diode 1 3 2√6 (8) |   16 6   1.5 The output capacitor current has high frequency and low frequency components. The low frequency component is simply calculated by: √ √ (10) And the high frequency RMS ripple current component is: 1.5 (9)   (11) The same method was used to derive RMS current in different topologies. Table 1 shows a summary of component
  • 4. Bridgeless Boost 8.1W 0.0W 0.0W 8.1W 21.6W 6.9W 9.8W 6.9W 9.7W 0W 0.0W 10 5.4W 10.8W 30 20 28.7W Bridgeless Interleaved Boost 10.8W 30.0W 30.0W Interleaved Boost 40 Device / Total Losses  25 Total Losses Intrinsic Body Diodes FETs Fast Diodes 0 Regular Diodes Also the low frequency RMS ripple current through output capacitors is constant and interleaving has no effect on it. But the high frequency ripple current will be reduced significantly, as it is shown in Figure 5. Also it is noted that as the input voltage increases, the high frequency ripple reduces. Conventional Boost 50 Power  Losses (W) As can be noted, in both the bridgeless topology and bridgeless interleaved topology, a new loss has been introduced in the intrinsic body diodes of the FETs, but since input bridge rectifiers were eliminated, there is some efficiency gain in overall performance of these topologies. The intrinsic body diode of FETs conduct when the boost transistors are off and its value is the same as the current in the boost diodes, when they conduct and transfer energy to the output capacitors. 60 47.7W 39.4W 42.3W RMS current stress for conventional boost converter and bridgeless boost converter. Table 2 provides the same summary for interleaved boost converter and bridgeless interleaved boost converter. Figure 6: Loss distribution in semiconductors High Frequency Capacitor Ripple Current in Conventional PFC 18.75 High Frequency Capacitor Ripple Current in IL PFC VI. EXPERIMENTAL RESULTS A prototype of the bridgeless interleaved converter circuit was built to verify proof-of-concept and analytical work presented in this paper as shown in Figure 7. The performance was compared with a benchmark interleaved boost converter. Ripple 12.5 (A) 6.25 Low Frequency Capacitor Ripple Current 0 0 75 150 225 300 Vin (V) Figure 5: RMS ripple current through output capacitors vs input voltage V. LOSS EVALUATION Figure 6 shows the loss distribution of the semiconductors in the four topologies investigated in this paper. The regular diodes in input bridge rectifiers have the largest share of losses among the topologies with the input bridge rectifier. The bridgeless topologies eliminate this large loss component (~30W). However, the tradeoff is that the FET losses are higher and the intrinsic body diodes of FETs conduct, producing new losses (~8W). The fast diodes in the conventional and interleaved PFC have slightly lower power losses, since the boost RMS current is higher in these topologies. Overall the FETs are under more stress in bridgeless topologies, but the total loss for the proposed bridgeless interleaved boost are 40% lower than the benchmark conventional boost, 27% lower than the bridgeless boost and 32% lower than the interleaved boost . Since the bridge rectifier losses are so large, it was expected that bridgeless interleaved boost converter would have the least power losses among all four introduced topologies. Also it was noted that the losses in the input bridge rectifiers were 63% of total losses in conventional PFC converter and 71% of total losses in interleaved PFC converter. Therefore eliminating the input bridges in PFC converters is justified despite the fact that new losses are introduced. Figure 7: Breadboard prototype of BLIL PFC Table 3 shows the semiconductors and power components used in the 3.4 kW CCM experimental prototypes – an interleaved boost PFC converter and a bridgeless interleaved PFC converter. The prototypes were built for a universal acline input (85~265 V) RMS at 400 V output. Figures 8 to 11 show the converter efficiency versus output power for interleaved boost PFC converter and bridgeless interleaved boost PFC converter at different input voltages and the following test conditions: fsw = 70 kHz, Iin = 15 A and Vo = 400 V. Since the input current is kept constant at 15 A, the output power is varying from 1200 W for 90 V input, 1.7 kW for 120 V input, 3 kW for 220 V input and 3.4 kW for 240 V input voltage. As it can be seen, for interleaved PFC the maximum efficiency of 97.5% is reached at 240 V input and around 2 kW output power. But as the input voltage reduces,
  • 5. TABLE III. DEVICES/COMPONENTS USED IN PROTOTYPE UNITS Device Part # / Value # of devices 98 97 96 Interleaved PFC Converter 95 Bridgeless Interleaved PFC Converter Fast Diode IDB06S60C 2 MOSFET IPB60R099CP 2 Inductor 800 μH 2 Fast Diode CSD10060 4 MOSFET IPP60R099CP 4 Inductor 400 μH 4 94 3000 2500 2000 1500 1000 500 0 93 PFC Bridgeless 99 4 Interleaved PFC 25ETS08S Regular Diode Interleaved Topology 100 Efficiency (%) the overall efficiency drops significantly as expected, where it is around 94.5% for 90 V input. Also it is noticed that at lighter loads, especially for low input lines, converter efficiency drops as low as 91% for 100 W and 90 V input. Output Power (W) Figure 9: Efficiency vs. output power for Interleaved and Bridgeless Interleaved PFC Boost Converter at Vin = 220 V 100 99 98 Efficiency (%) 100 98 96 95 94 Interleaved PFC Converter Bridgeless Interleaved PFC Converter 93 97 Interleaved PFC Converter 92 1800 1600 1400 1200 1000 800 600 95 400 91 Bridgeless Interleaved PFC Converter 200 96 0 Efficiency (%) 99 97 Output Power (W) 100 96 95 94 93 92 91 1200 1000 800 90 600 A Yokogawa W230 digital power meter was used for efficiency measurements. A Chroma 63202 DC electronic load and an Agilent 6834B AC source/Analyzer were also used in the experiments. Bridgeless Interleaved PFC Converter 97 0 For bridgeless interleaved PFC, the overall efficiency drops at lower input voltages as expected, where it is around 96% for 90 V input. 98 Efficiency (%) But a higher maximum efficiency of 98.5% was reached at 240 V input and around 2 kW output power for bridgeless interleaved PFC converter. Also it is noticed that at lighter loads, especially for low input lines, converter efficiency is improved significantly (as high as 3% at 200 W) compared to interleaved boost converter. Interleaved PFC Converter 99 Figure 8: Efficiency vs. output power for Interleaved and Bridgeless Interleaved PFC Boost Converter at Vin = 240 V 400 Output Power (W) Figure 10: Efficiency vs. output power for Interleaved and Bridgeless Interleaved PFC Boost Converter at Vin = 120 V 200 3500 3000 2500 2000 1500 1000 500 0 94 Output Power (W) Figure 11: Efficiency vs. output power for Interleaved and Bridgeless Interleaved PFC Boost Converter at Vin = 90 V
  • 6. VII. CONCLUSION A new high efficiency bridgeless interleaved PFC AC-DC Boost converter topology has been presented in this paper. The target application for the converter is the front-end AC-DC converter in plug-in hybrid electric vehicle battery chargers. The proposed converter has been analyzed and its performance characteristics have presented. Also an analytical model for four different topologies was developed, enabling the calculation of power losses and efficiency calculation. A breadboard converter circuit has been built to verify the proofof-concept. The proposed converter shows a high efficiency (~98.5 %), especially for lighter loads and lower input voltages, high input power factor and excellent input current harmonics. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] K. Morrow, D. Karner, and J. Francfort, "Plug-in Hybrid Electric Vehicle Charging Infrastructure Review," U.S. Departent of Energy Vehicle Technologies Program, 2008. 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