VHDL

1. VHDL Examples
Eng.M.Atef.Elhusainy
Design and Simulation of
Electronic circuits
Lecture 02
Elc-sim-lec02

2. Basic Logic Gates
Elc-sim-lec02

3. Half Adder
Truth Table
Realize using NAND only
Logical Expression
Elc-sim-lec02
Eng.M.Atef.Elhusainy

4. Elc-sim-lec02
Eng.M.Atef.Elhusainy

5. Full Adder
Elc-sim-lec02
Eng.M.Atef.Elhusainy

6. 4*1 Multiplexer
Y=D0(not S1)(not S0)+D1(not S1)S0+D2S1(not S0)+D3S1S0
Elc-sim-lec02
Eng.M.Atef.Elhusainy

7. 8*1 Multiplexer
Enable Selector Output
E S2 S1 S0 Y
1 0 0 0 D0
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7
𝑌 = 𝐸. (𝑆2 𝑆1 𝑆0𝐷0 + 𝑆2 𝑆1 𝑆0𝐷1 + 𝑆2 𝑆1𝑆0𝐷2 + 𝑆2 𝑆1𝑆0𝐷3 + S2 𝑆1 𝑆0𝐷4
+𝑆2𝑆1 𝑆0𝐷5 + S2 𝑆1𝑆0𝐷6 + S2𝑆1𝑆0𝐷7 )
Elc-sim-lec02
Eng.M.Atef.Elhusainy

8. Elc-sim-lec02
Eng.M.Atef.Elhusainy

9. Elc-sim-lec02
Eng.M.Atef.Elhusainy