AXI is an on-chip, point to point communication protocol. It is used as a high-performance bus in various IP or SoC Systems. It is used for connecting high-performance processors with memory.
5. Features of AXI
5 Channels (Write address, Write data, Write Response, Read data/response,
Read address )
No strict timing relationship between address and data signal
On chip, Point to Point Communication protocol
Multiple Outstanding(Multiple request)
Burst based transactions with only start address issued
Aligned and non-aligned address support
Out of order
Data interleaving
Atomicity(Locked and Exclusive Excess)
128 byte data bus width support
Maximum 256 beat transfers in AXI4, 16 beat(AXI3)
QoS(Quality of Support), Cache, Protection, User support
8. AXI INTERCONNECT
Components and its uses:-
Arbiter (Multiple master select)
Decoder(Multiple slave select)
Multiplexers(write and read data channels)
Clock converter(PLL)
Register slices(5) consist of Dff and Mux
9. AXI SIGNALS
Write Address (AW) channel
signals
AXI version
AWVALID AXI3 and AXI4
AWREADY AXI3 and AXI4
AWADDR[31:0 AXI3 and AXI4
AWSIZE[2:0] AXI3 and AXI4
AWBURST[1:0] AXI3 and AXI4
AWCACHE[3:0] AXI3 and AXI4
AWPROT[2:0 AXI3 and AXI4
AWID[x:0] AXI3 and AXI4
AWLEN[3:0]
AWLEN[7:0]
AXI3 only
AXI4 only
AWLOCK[1:0]
AWLOCK
AXI3 only
AXI4 only
AWQOS[3:0] AXI4 only
AWREGION[3:0] AXI4 only
AWUSER[x:0] AXI4 only
Write Data (W) channel
signals
AXI version
WVALID AXI3 and AXI4
WREADY AXI3 and AXI4
WLAST AXI3 and AXI4
WDATA[x:0] AXI3 and AXI4
WSTRB[x:0] AXI3 and AXI4
WID[x:0] AXI3 only
WUSER[x:0 AXI4 only
Write Response (B) channel
signals
AXI version
BVALID AXI3 and AXI4
BREADY AXI3 and AXI4
BRESP[1:0 AXI3 and AXI4
BID[x:0] AXI3 and AXI4
BUSER[x:0 AXI4 only
10. Read address and data signals
Read Address (AR) channel
signals
AXI version
ARVALID AXI3 and AXI4
AREADY AXI3 and AXI4
ARADDR[31:0 AXI3 and AXI4
ARSIZE[2:0 AXI3 and AXI4
ARBURST[1:0 AXI3 and AXI4
ARCACHE[3:0 AXI3 and AXI4
ARPROT[2:0 AXI3 and AXI4
ARID[x:0 AXI3 and AXI4
ARLEN[3:0]
ARLEN[7:0]
AXI3 only
AXI4 only
ARLOCK[1:0]
ARLOCK
AXI3 only
AXI4 only
ARQOS[3:0 AXI4 only
ARREGION[3:0 AXI4 only
ARUSER[x:0 AXI4 only
Read Data (R) channel
signals
AXI version
RVALID AXI3 and AXI4
READY AXI3 and AXI4
RLAST AXI3 and AXI4
RDATA[x:0] AXI3 and AXI4
RRESP[1:0] AXI3 and AXI4
RID[x:0] AXI3 and AXI4
RUSER[x:0] AXI4 only
The following table shows the Read Data channel signals:
11. Channel Handshaking
Valid = 1 means valid packet is being transferred
Ready indicates whether slave is ready or not to receive the next transaction
To complete 1 transfers valid = 1, ready = 1
12. Deadlock Conditions
Data interleaving – To avoid deadlock slave interface which supports write data interleaving must
accept interleaved data. It must never stall the acceptance of write data in a attempt to change
the order of write data
Read bust transactions require a response for each beat of burst and correctly inserted RLAST to
avoid deadlock
Write burst transaction require a response at last beat of burst and correctly inserted WLAST to
avoid deadlock
Master must not wait for the AWREADY to be asserted before driving WVALID. A deadlock condition
can occur if a slave is waiting for WVALID before asserting AWREADY
13. Transaction handshake dependencies
Read response always come after read data
Read data always come after Read
address
Write data can appear before Write
address
In AXI3 address does not have to be sent
before write response is sent
In AXI4 address have to be sent before
read response
Write response always come after write
data
17. Burst control signals
.
Burst
length(AXI3)
Burst Size Burst Type
Every transaction must have
the number of transfers
No component can terminate a
burst early to reduce the
number of data transfers.
18. Burst
Value Burst type Usage notes
Length (number of
transfers)
Alignment
0x00 FIXED
Reads the same address repeatedly. Useful
for FIFOs.
1-16
Fixed byte lanes only
defined by start address
and size.
0x01 INCR
Incrementing burst.
The slave increments the address for each
transfer in the burst from the address for the
previous transfer.
The incremental value depends on the size
of the transfer, as defined by the AxSIZE
attribute.
Useful for block transfers.
AXI3: 1-16
AXI4: 1-256
Unaligned transfers are
supported.
0x10 WRAP
Wrapping burst.
Similar to an incrementing burst, except that
if an upper address limit is reached, the
address wraps around to a lower address.
Commonly used for cache line accesses.
2, 4, 8, or 16
The start address must
be aligned to the
transfer size.
0x11 RESERVED Not for use. - -
19. Cont..
For INC burst starting address can be unaligned while henceforth address will be aligned automatically by slave
For wrap burst starting address is aligned , if unaligned address is given then it will be aligned
aligned address = INT(start address/total byte transfer)*total byte transfer
Wstrobe defines the valid data in a data bus
Wrap boundary calculation:-
lower byte lane = start address – (start address % total byte transfer)
upper byte lane = lower byte lane + total byte transfer
Ex- size = 4 , length = 3 , starting address = 4 , AWBURST = 10(wrap) , 32 bit bus
total transfer byte = 16 byte
lower byte lane = 4 – (4%16) = 0
upper byte lane = 16(wrap boundry)
wrap boundary and strobe calculation -
7 6 5 4
b a 9 8
f e d c
3 2 1 0
20. Response Signaling
Response code Description
00 - OKAY
Normal access success or exclusive access failure.
OKAY is the response that is used for most transactions. OKAY
indicates that a normal access has been successful.
This response can also indicate that an exclusive access has
failed. An exclusive access is when more than one master can
access a slave at once, but these masters cannot access the
same memory range.
01 - EXOKAY
Exclusive access okay.
EXOKAY indicates that either the read or write portion of an
exclusive access has been successful.
10 – SLVERR
Slave error.
SLVERR is used when the access has reached the slave
successfully, but the slave wants to return an error condition to the
originating master.
This indicates an unsuccessful transaction. For example, when
there is an unsupported transfer size attempted, or a write access
attempted to read-only location.
11 - DECERR
Decode error.
DECERR is often generated by an interconnect component to
indicate that there is no slave at the transaction address.
21. Aligned/Unaligned transfers
Aligned transfer means each address is aligned with the size of data bus.
Unaligned transfer means address is not completely aligned with the size of data bus
Note – To achieve the aligned transfers address must be the multiple of size.
For ex- address = 3 , size – 8 - Unaligned
address = 10, size – 4 - Unaligned
address = 50 , size – 8 – Unaligned
address = 20, size – 4 - Aligned
address – 16, size – 2 - Aligned
Starting address is issued by master while subsequent aligned address will be
calculated by slave which is
starting address + size
22. . 1
Aligned Transfer
7 6 5 4 3 2 1 0
Address: 0x00
Transfer size: 32 bits
Burst type: incrementing
Burst length: 4 transfers
64-bit write data bus
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0
F E D C B A 9 8
7 6 5 4 3 2 1 0F E D C B A 9 8
WSTRB 0 0 0 0 1 1 1 1
WSTRB
1
1 1 1 0 0 0 0
For wrapping burst type, all
transfers are aligned transfers
11
1 11
11
1
23. Unaligned Transfer
.
7 6 5 4 3 2 1 0
Address: 0x07
Transfer size: 32 bits
Burst type: incrementing
Burst length: 4 transfers.
64-bit write data bus
63 56 55 48 47
40 39 32 31 24 23 16 15 8 7 0
7 6 5 4 3 2 1 0F E D C B A 9 8
7 6 5 4 3 2 1 0F E D C B A 9 8
17 16 15 14 13 12 11 10
WSTRB 1 0 0 0 0 0 0 0
WSTRB 0 0 0 0 1 1 1 1
For incrementing burst type, fist
transfer can be unaligned
transfers, but the rest transfers are
aligned transfers
1 1 1 1
1 1 1 1
24. Out of order/Data interleaving
.
A11 A21 A31
Out of Order CompletionD21
Wait
Cycle D22 D23 D11 Wait
Cycle D12 D13 D14 D31
D21 D31 D22 D23 D11 D32 D12 D13 D14
Data Interleaving
D31 D11 D32 D12 D13 D33 D14
A11 A31
D41 D21 D22 D23 D24
B33 D14
A21 A41
Write Address Channel
Read Address Channel
Write Data Channel
Read Data Channel
Write Response Channel
Out of Order Completion
Write data channel
Read data channel
Data Interleaving
• Write data channel
. AXI4 does not
support write data
Interleaving due to
absence of WID
25. Atomic Accesses
00 – Normal
01 – locked
10- Exclusive accesses
11- Reserved
Note – AXI4 does not support locked and Reserved accesses
Locked Access :-
1. M0 initiates read, modify write sequence
2. Interconnect locks out other transaction
3. Interconnect removes the lock when sequence
Completes.
Master can lock either read or write sequence first
26. Exclusive Accesses
Master must initiates read ,modify, write sequence
Read and write address must be same
Exclusive operation is performed at corresponding AWID and ARID
Exclusive excess fails is another master has written to the memory region
Failed Exclusive access -> Okay response, Success Exclusive access -> EXOKAY
27. Cache support
1. AxCACHE[0] – Bufferable bit
If transaction is bufferable then Bridge, System level cache, Interconnect or any other component may
delay the transaction and gives write response
If transaction is non-bufferable then end point slave will give response
2. AxCACHE[1] – cacheable bit (AXI3), Modifiable bit(AXI4)
Attribute of the final transactions do not have to match with the attribute of original transaction
Writes – Several writes can merge or a single write can be broken into multiple transactions
Reads – Content of location can be perfected or values from the sig]le fetch can be used for multiple
read transactions
28. Cont..
3. AxCACHE[2] – RA bit
If transfer is read and its misses in cache then it should be allocated
4. AxCACHE[3] – RA bit
If transfer is write and its misses in cache then it should be allocated
Note – if AxCACHE][1] is not inserted then AxCACHE[2], AxCACHE[3] cannot be inserted.
29. Protection Support
To support the complex design , for the interconnect and other devices in the system to provide protection
against illegal transactions
1. AxPROT[0]
. 1 indicate privileged mode (first priority)
. 0 indicates normal mode
AXI
Master1
CPU AXI
Interconnect
AXI
Slave1
AXI
Slave2
AXI
Master2
Normal
access
Privileged
access
Normal
access
30. Cont..
2. AxPROT[1]
. 1 indicates non secure access
. 0 indicates secure access
It is used in the system where greater degreed of differentiation between processing mode is required
Non-secure
AXI
Slave1
(Secure)Secure
AXI
Interconnect
AXI
Master1
AXI
Slave2
(Non-secure)
AXI
Slave3
(Non-secure)
SLVERR response
OKAY response
DECERR response
Non-secure slave
disappears from the
memory map during
secure accesses
31. Cont..
3. AxPROT[2] :- Data/ Instructions
This bit gives an indication if the transaction is an instruction or data access
When a transaction contains a mix of
instruction and data items
It’s recommended that, by default, an access is
marked as a data access unless specifically known to
be an instruction access
Instruction Data Data
32. QoS(Quality of service )
Prioritize transactions, Improve system performance
AWQoS, ARQoS
33. Region/user Signaling
Region:-
Single physical interface can on a slave can provide multiple logical interface
Slave does not have to support the address decode between the different logical interface
AWREGION, ARREGION
User:-
It is used in all channels to transfer customized signal between master and slave
Ex- adding parity