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                July 2008
Jiri Ocenasek, Magwel NV, Belgium                     1
Robust circuit sizing:
   EDA for EDA




  Jiri Ocenasek, Magwel NV, Belgium                     2
Company Overview



    MAGWEL was founded in April 2003

    Spin­off from IMEC in Belgium

    Initially focused on 3D device­EM simulation

    With acquisition of Kimotion Technologies
     −   Expanding into Robust Design and Verification of Analog 
         and RF circuits

    Customers: TI, NXP, IMEC, UCL ….

    Participant in EU research projects
                 Jiri Ocenasek, Magwel NV, Belgium                     3
Robust sizing of Analog & RF building blocks

 Design variables           Specifications       Process and Environment




                                                     EldoTM
                                                     SpectreTM
                                                     HspiceTM
                                                     KtModels
                                                     ADVanceMSTM
                                                     …




Performance models        Optimized netlist         Specification corners


                Jiri Ocenasek, Magwel NV, Belgium                     4
Example: Gain­boosted op. amplifier
* [M.Waltari, “circuit techniques for low-voltage and high-speed A/D converters, PhD.]




         Jiri Ocenasek, Magwel NV, Belgium                     5
Terminology I


    Design variables                                         D
    −   The designer can prescribe them within some accuracy
    −   Example: W and L of transistors, bias current, …

    Operational variables                                    O
    −   The circuit has to work under all operational conditions within 
        specified limits
    −   Example: Temperature, Supply voltage, …

    Technology variables                                     T
    −   Variation of manufacturing process, statistically distributed
    −   Example: Doping parameters of substrate
                   Jiri Ocenasek, Magwel NV, Belgium                     6
Terminology II

    Mismatch variables                                   M


                                                     Mismatch in T


                                                           +
                                                      Mismatch in D




            IDS1            IDS2                    Transistors are not 
                                                         identical !
    VGS1                             VGS2
               Jiri Ocenasek, Magwel NV, Belgium                     7
Terminology III


    Response variables                                      R
    −   Extracted from simulator’s output: r = simulate(d,o,t,m )
    −   Example: Noise, Gain, Power, Die area, ...
   Constraint cost for i­th constraint        Ci(r)
    ­   Ci(r) ≥ 0  if satisfied,      Ci(r) < 0  if violated
    ­   Example: Power is below 100 mW: “100mW ­ Power”
   Goal cost for j­th goal                                 Gj(r)


                  Jiri Ocenasek, Magwel NV, Belgium                     8
Yield explanation


    Probability density function    ρ(t,m )
    ­   Typically normal or uniform

    Advanced manufacturing processes ­ the design d 
    has to be robust against variations of t and m
    ­   yield(d) = ∫t,m  F(d,t,m) ρ(t,m) dt dm
    where F(d,t,m) indicates whether all constraints Ci are 
     satisfied under all permissible operational conditions o:
            F(d,t,m)=1     if    ∀i, ∀ο ϵΟ : Ci(simulate(d,o,t,m))≥0
         
             F(d,t,m)=0     otherwise
                     Jiri Ocenasek, Magwel NV, Belgium                     9
Optimization target


    First stage: nominal optimization
    −   find d such that ∀i: Ci(simulate(d,o=nominal,t=0,m=0))≥0
    −   can be replaced by user­provided solution

    Second stage: yield maximization
    −   find/improve d such that yield(d) is maximized

    Third stage: when yield( d ) > 0.997
    −   minimize sum of goals ∑j Gj(d,o=nominal,t=0,m=0,r) 
        while keeping the yield

                  Jiri Ocenasek, Magwel NV, Belgium                     10
Results: gain­boosted amplifier

# devices                                                  56
# design variables                                         22
# constraints                                              63
# tech.+mm. variables                                      30
# operational variables                                     4
starting point                                          none

# simulations                                          12626
runtime                                              251 min
total yield                                            99.8%
goal 1                                      area = 7970 μm2
goal 2                                     power = 13.7 mW

         Jiri Ocenasek, Magwel NV, Belgium                     11
Results: gain­boosted amplifier


  Number of fitness evaluations




  Jiri Ocenasek, Magwel NV, Belgium                     12
Jiri Ocenasek, Magwel NV, Belgium                     13
Why are Estimation of Distribution 
                   Algorithms suitable?


    Decomposability of the problem
    −   the circuit is composed of sub­blocks

    Complicated fitness landscape
    −   multimodality: several local optima
    −   nonlinearities: responses are hard to be modeled
    −   discontinuities: simulator switches modes
    −   missing data: regions where simulation fails


               Jiri Ocenasek, Magwel NV, Belgium                     14
Conclusion


    Robust Optimizer
     −   Can handle tough circuits where others fail
     −   Capable of handling fairly large blocks

    Produces quality results with high yield
     −   3 step approach, does not require user intervention
     −   Provides insight: yield distributions, sensitivities, trade­offs

    Integration
     −   Cadence design environment
     −   Simulators: Spectre, Eldo, Hspice (others can be added)
     −   Supports LSF for distributed simulation

                     Jiri Ocenasek, Magwel NV, Belgium                     15
Thank you




Jiri Ocenasek, Magwel NV, Belgium                     16

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Robust-Circuit-Sizing:-EDA-for-EDA

  • 1. + July 2008 Jiri Ocenasek, Magwel NV, Belgium                     1
  • 2. Robust circuit sizing: EDA for EDA Jiri Ocenasek, Magwel NV, Belgium                     2
  • 3. Company Overview  MAGWEL was founded in April 2003  Spin­off from IMEC in Belgium  Initially focused on 3D device­EM simulation  With acquisition of Kimotion Technologies − Expanding into Robust Design and Verification of Analog  and RF circuits  Customers: TI, NXP, IMEC, UCL ….  Participant in EU research projects Jiri Ocenasek, Magwel NV, Belgium                     3
  • 4. Robust sizing of Analog & RF building blocks Design variables Specifications Process and Environment EldoTM SpectreTM HspiceTM KtModels ADVanceMSTM … Performance models Optimized netlist Specification corners Jiri Ocenasek, Magwel NV, Belgium                     4
  • 5. Example: Gain­boosted op. amplifier * [M.Waltari, “circuit techniques for low-voltage and high-speed A/D converters, PhD.] Jiri Ocenasek, Magwel NV, Belgium                     5
  • 6. Terminology I  Design variables  D − The designer can prescribe them within some accuracy − Example: W and L of transistors, bias current, …  Operational variables O − The circuit has to work under all operational conditions within  specified limits − Example: Temperature, Supply voltage, …  Technology variables T − Variation of manufacturing process, statistically distributed − Example: Doping parameters of substrate Jiri Ocenasek, Magwel NV, Belgium                     6
  • 7. Terminology II  Mismatch variables M Mismatch in T + Mismatch in D IDS1 IDS2 Transistors are not  identical ! VGS1 VGS2 Jiri Ocenasek, Magwel NV, Belgium                     7
  • 8. Terminology III  Response variables R − Extracted from simulator’s output: r = simulate(d,o,t,m ) − Example: Noise, Gain, Power, Die area, ...  Constraint cost for i­th constraint        Ci(r) ­ Ci(r) ≥ 0  if satisfied,      Ci(r) < 0  if violated ­ Example: Power is below 100 mW: “100mW ­ Power”  Goal cost for j­th goal         Gj(r) Jiri Ocenasek, Magwel NV, Belgium                     8
  • 9. Yield explanation  Probability density function    ρ(t,m ) ­ Typically normal or uniform  Advanced manufacturing processes ­ the design d  has to be robust against variations of t and m ­ yield(d) = ∫t,m  F(d,t,m) ρ(t,m) dt dm where F(d,t,m) indicates whether all constraints Ci are  satisfied under all permissible operational conditions o:  F(d,t,m)=1     if    ∀i, ∀ο ϵΟ : Ci(simulate(d,o,t,m))≥0  F(d,t,m)=0     otherwise Jiri Ocenasek, Magwel NV, Belgium                     9
  • 10. Optimization target  First stage: nominal optimization − find d such that ∀i: Ci(simulate(d,o=nominal,t=0,m=0))≥0 − can be replaced by user­provided solution  Second stage: yield maximization − find/improve d such that yield(d) is maximized  Third stage: when yield( d ) > 0.997 − minimize sum of goals ∑j Gj(d,o=nominal,t=0,m=0,r)  while keeping the yield Jiri Ocenasek, Magwel NV, Belgium                     10
  • 11. Results: gain­boosted amplifier # devices 56 # design variables 22 # constraints 63 # tech.+mm. variables 30 # operational variables 4 starting point none # simulations 12626 runtime 251 min total yield 99.8% goal 1 area = 7970 μm2 goal 2 power = 13.7 mW Jiri Ocenasek, Magwel NV, Belgium                     11
  • 12. Results: gain­boosted amplifier Number of fitness evaluations Jiri Ocenasek, Magwel NV, Belgium                     12
  • 14. Why are Estimation of Distribution  Algorithms suitable?  Decomposability of the problem − the circuit is composed of sub­blocks  Complicated fitness landscape − multimodality: several local optima − nonlinearities: responses are hard to be modeled − discontinuities: simulator switches modes − missing data: regions where simulation fails Jiri Ocenasek, Magwel NV, Belgium                     14
  • 15. Conclusion  Robust Optimizer − Can handle tough circuits where others fail − Capable of handling fairly large blocks  Produces quality results with high yield − 3 step approach, does not require user intervention − Provides insight: yield distributions, sensitivities, trade­offs  Integration − Cadence design environment − Simulators: Spectre, Eldo, Hspice (others can be added) − Supports LSF for distributed simulation Jiri Ocenasek, Magwel NV, Belgium                     15