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CXL 2.0/3.x Switch Enabling Composable
Memory Architecture in AI/HPC Computing
CXL 2.0/3.x Switch Enabling Composable
Memory Architecture in AI/HPC Computing
Gerry Fan, President and CEO, XConn Technologies Inc
Composability and Disaggregation
Enabled by Switches
In-Memory HPC Compute Apps
Tiering/Pooling/Sharing
CXL 1.1/2.0 Switches
AI GPU/Accelerators
Pooling/Sharing/Fabric
CXL 3.x Switches
2015 2023 2026
SSD/NIC/GPU
SRIOV Pooling
PCIe Switches
Technology
Trend
/
Leader
CXL Enables DRAM Usage
Optimization
4
Host 1 Host 2 Host 3
CXL Switch
Host 1 Host 2 Host 3
JBO
M
Multiple Heterogenous Servers
Each With Dedicated DRAM CXL Enabled Memory Pooling / Sharing
Scalable Memory Pooling/Sharing
Enabled by CXL Switch
5
Memory Pooling/Sharingwith
CXL 1.1 Hostsand Single Logical Devices
H
#
H
1
H
3
H
4
H
2
D
#
D
1
D
3 D
4
D
2
CXL2.0Switch
Memory Pooling with CXL 2.0 Hosts and
Multiple Logical Devices
D
#
H
#
D
1
H
1
D
3
H
3
D
4
H
4
D
2
H
2
CXL2.0Switch
Management Host
(CXLFabricManager)
Management Host
(CXLFabricManager)
CXL 3.1 AI Memory Sharing/Pooling
GPU
HOST 0
XC60256
FMM (FabricManager
Module)
vCXL
vCXL vCXL
HOST 1
vCXL
vCXL vCXL
HOST N
vCXL
vCXL vCXL
CXL CXL CXL
MGMT
Processor
GPU GFAM
FM
Manager
SW
Peer to Peer (UIO/
MMIO)
Peer to Peer (UIO/
MMIO)
HBM/DDR HBM/DDR
CXL.mem + Back-
Invalidate
CXL Memory Pooling/Sharing System
CXL
Host 0
FM Host/
Management Host
CXL
Host 1
…
Xconn Ref. Boards
(EDSFF/CEM Expander Chassis)
D0 D1 Dn
D2
PCIe/I2C/UART
Xconn Ref. Board
(Apollo Silicon)
• Industry consensus is CXL memory pooling & sharing will be
the early application to ramp CXL usage in AI/HPC
• XConn is accelerating the adoption of this application with CXL
2.0/CXL3.1 Switches
• XConn is helping the CXL eco-system mature earlier by working
with all the CPU, Memory & Software partners and
demonstrating interoperability between the eco-system players
How to Accelerate CXL Adoption
XConn Product Timeline
2023 2024 2025 2026
JBOG, JBOA,
Data Center,
HPC,
AI/DL/ML
CXL Switch
for Memory
Pooling and
PCIe Switch
for
Connectivity
CXL 2.0 & PCIe 5.0
CS – March, 2023
XC60256
XC61256
CXL 3.1 & PCIe 6.1
CS – 1Q25
XC50256
XC51256
CXL 2.0 & PCIe 5.0
MP – 2Q24
Apollo II
XC50256
XC51256
Apollo I
XC60256
XC61256
CXL 3.1 & PCIe 6.1
MP – 2Q26
For product ordering, please visit www.xconn-tech.com
Thank you!

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CXL 2.0/3.x Switch Enabling Composable Memory Architecture in AI/HPC Computing

  • 1. CXL 2.0/3.x Switch Enabling Composable Memory Architecture in AI/HPC Computing
  • 2. CXL 2.0/3.x Switch Enabling Composable Memory Architecture in AI/HPC Computing Gerry Fan, President and CEO, XConn Technologies Inc
  • 3. Composability and Disaggregation Enabled by Switches In-Memory HPC Compute Apps Tiering/Pooling/Sharing CXL 1.1/2.0 Switches AI GPU/Accelerators Pooling/Sharing/Fabric CXL 3.x Switches 2015 2023 2026 SSD/NIC/GPU SRIOV Pooling PCIe Switches Technology Trend / Leader
  • 4. CXL Enables DRAM Usage Optimization 4 Host 1 Host 2 Host 3 CXL Switch Host 1 Host 2 Host 3 JBO M Multiple Heterogenous Servers Each With Dedicated DRAM CXL Enabled Memory Pooling / Sharing
  • 5. Scalable Memory Pooling/Sharing Enabled by CXL Switch 5 Memory Pooling/Sharingwith CXL 1.1 Hostsand Single Logical Devices H # H 1 H 3 H 4 H 2 D # D 1 D 3 D 4 D 2 CXL2.0Switch Memory Pooling with CXL 2.0 Hosts and Multiple Logical Devices D # H # D 1 H 1 D 3 H 3 D 4 H 4 D 2 H 2 CXL2.0Switch Management Host (CXLFabricManager) Management Host (CXLFabricManager)
  • 6. CXL 3.1 AI Memory Sharing/Pooling GPU HOST 0 XC60256 FMM (FabricManager Module) vCXL vCXL vCXL HOST 1 vCXL vCXL vCXL HOST N vCXL vCXL vCXL CXL CXL CXL MGMT Processor GPU GFAM FM Manager SW Peer to Peer (UIO/ MMIO) Peer to Peer (UIO/ MMIO) HBM/DDR HBM/DDR CXL.mem + Back- Invalidate
  • 7. CXL Memory Pooling/Sharing System CXL Host 0 FM Host/ Management Host CXL Host 1 … Xconn Ref. Boards (EDSFF/CEM Expander Chassis) D0 D1 Dn D2 PCIe/I2C/UART Xconn Ref. Board (Apollo Silicon)
  • 8. • Industry consensus is CXL memory pooling & sharing will be the early application to ramp CXL usage in AI/HPC • XConn is accelerating the adoption of this application with CXL 2.0/CXL3.1 Switches • XConn is helping the CXL eco-system mature earlier by working with all the CPU, Memory & Software partners and demonstrating interoperability between the eco-system players How to Accelerate CXL Adoption
  • 9. XConn Product Timeline 2023 2024 2025 2026 JBOG, JBOA, Data Center, HPC, AI/DL/ML CXL Switch for Memory Pooling and PCIe Switch for Connectivity CXL 2.0 & PCIe 5.0 CS – March, 2023 XC60256 XC61256 CXL 3.1 & PCIe 6.1 CS – 1Q25 XC50256 XC51256 CXL 2.0 & PCIe 5.0 MP – 2Q24 Apollo II XC50256 XC51256 Apollo I XC60256 XC61256 CXL 3.1 & PCIe 6.1 MP – 2Q26 For product ordering, please visit www.xconn-tech.com

Editor's Notes

  1. host