Apresentação feita em 2006 no Annual Simulation Symposium.

39th Annual Simulation Symposium

Modeling, Simulation and Performance
Evaluation for a CIOQ Switch
Architecture
Sebastiao R. de Aguiar Filho
Antonio M. Alberti FEMC – Fundação Educacional Montes Claros,
INATEL – National Institute of MG, Brazil.
Telecommunications, MG, Brazil. Anilton Salles Garcia
UFES – Federal University of Espirito Santo,
ES, Brazil.
Sponsored by FAPEMIG


Presentation Outline
Introduction
Single Input Buffer CIOQ Architecture
Class Based Input Buffer CIOQ Architecture
Developed Models
Performance Evaluation
Final Remarks


Introduction
In the past decade, data traffic has experimented a huge
growth, mainly due to Internet popularization.

Telephony operators built new networks to transport end
users multimedia traffic.

Technologies as ADSL and ATM (Asynchronous Transfer
Mode) emerged in access and core networks, respectively.

Also, powerful routers have been developed to drain Internet
traffic.


Introduction
Packet switching nodes and their architectures have
experienced a big development, not only in terms of capacity
and scalability, but also in terms of efficiency and QoS
support.

An important portion of this deployment occurred in the
context of the ATM networks.

Most of the ATM switch architectures are built arranging
multistage switching elements to form an interconnection
network.


Introduction
They can be classified as:
Blocking or non-blocking, according to their capacity to control
packet loss events or to eliminate blocking.
Input-Queueing (IQ), Output-Queueing (OQ) or Shared-
Queueing (SQ), depending on where buffering is necessary.

Output-Queueing:
Advantage:
It has 100% theoretical throughput.
Disadvantages:
It requires an internal speedup factor in order to transfer several packets to
a single output queue in every cycle.
Output queues capacity must be large enough to store all the transferred
packets.


Introduction
Input-Queueing:
Advantage:
Overcomes the scalability problem, because they run as fast as the input
line rate, therefore making possible to build very fast switches.
Disadvantages:
It requires an internal speedup factor in order to transfer several packets to
a single output queue in every cycle.
Suffers from HOLB (Head-of-Line-Blocking), which limits the throughput to
just 58.6%.

Virtual Output Queueing (VOQ):
Advantage:
Eliminates HOLB.
Disadvantage:
High complexity and poor scalability, since the number of virtual queues in
the input ports grows quadradically with the number of input ports.


Introduction
Combined Input/Output Queue (CIOQ):
Advantage:
Combines input and output queueing and achieves a good balance
between performance and scalability.
Capable to remove S packets from each input port and transfer up to S
packets to every output during an input time slot.

Disadvantage:
According to Luo et.al., CIOQ is very complex when compared with CICQ
(Combined Input-Crosspoint-Queueing).


Introduction
Santos-Motoyama (SM) CIOQ:
Advantages:
Doesn’t need internal speedup.
Can reduce HOLB while improving throughput.
More simple than original CIOQ.

These features motivated us to model, simulate and evaluate
SM CIOQ architectures. Also, we are interested on validate and
compare results with original SM paper.

Santos-Motoyama developed two CIOQ Architectures:
Class Based CIOQ Architecture


It has one simple FIFO queue for each input port, a crossbar
with m internal links (or channels) from each input to each
output port and m output queues in every output port.
Each input queue has a control unit (CRT), which monitors
queue’s head in order to determine if there exists a packet to
be transferred.

If it is the case, it sends a request (REQ) to a desired output
port scheduler module (SCH) in order to request a crossbar
link to this output port.
Any CRT can ask just one request per time slot.


REQ Bus
Overview (N bits)
SCH 1 SCH 2 SCH N
ACK Bus
(N bits)

CRT 1
Input
Port 1

CRT 2
Input
Port 2

CRT 3
Input
Port 3

CRT 4 1 2 m 1 2 m 1 2 m
Input
Port 4

CRT N
Input
Port N

1 2 m 1 2 m 1 2 m
Output Output Output
Port 1 Port 2 Port N


The SCH grants on a round-robin basis up to m links to the
asking CRTs.

This is done through acknowledgement signals (ACKs).

To be fair, in the next cycle SCH will begin to grant from the
input that wasn’t granted in the previous cycle.

The output queues are also served in a round-robin basis.


Extended version of the previous architecture to support
traffic classes priorization.

It has five logical FIFO queues in each input port, one for
every priority class.

The priority classes are named according to ATM service
categories: CBR, rtVBR, nrtVBR, ABR and UBR.

The incoming packets are classified and stored in the
appropriate class queues.


The architecture also uses two buses: REQ and ACK.

At each output port, 5xm physical queues are needed, where
m is the number of internal links.

Also, it has one scheduler for each output port.

Both input and output schedulers use round-robin service
discipline to determine service order.


REQ Bus
(N bits)
Overview ACK Bus
SCH 1 SCH N

(N bits)

CRT 1

CBR

rtVBR
Input nrtVBR
Port 1
ABR

UBR

CRT 2

CBR

rtVBR
Input nrtVBR
Port 2
ABR

UBR

1 m 1 m
CRT N

CBR

rtVBR
Input nrtVBR
Port N
ABR

UBR
nrtVBR

nrtVBR

nrtVBR

nrtVBR
rtVBR

rtVBR

rtVBR

rtVBR
ABR

ABR
UBR

CBR

UBR

CBR

UBR

CBR

UBR

CBR
ABR

ABR

Output Output
Port 1 Port N


Developed Models
We used Arena 5.0TM to develop and implement simulation
models for the SM CIOQ architectures.

To each architecture we developed a basic model and
implemented several derived models varying the number of
input-output ports (N), the number of internal links (m) and the
offered load (r).

At the end, we developed 181 simulation models.

Model Example: N8M2R09 (N=8, m=2 and r=0.9) single
buffer CIOQ model.


Developed Models
N8M2R09 ArenaTM Model


Developed Models
N8M2R09 Block Diagram
Cell Load Output Port Input Port Schedulers and Crossbar
Generation Regulation Definition Queues

Create 1 Decide 28 Assign 1 Hold 1
Decide 2 Assign 17
Assign 9 Process 81

Create 2 Decide 29 Assign 2 Hold 2
Decide
Decide 1 Assign 10 Decide 3 Assign 18 Process 82
10

Create 8 Decide 35 Assign 8 Hold 8 Process 88

Assign 16 Decide 9 Assign 24

Dispose
3

Process
Create 10 Delay 100
Assign 73 Process 9 Assign 25 100
Output Ports

Assign 82
Assign 81 Assign 74 Process 10 Assign 26

Dispose Dispose
1 Assign 80 Process 16 Assign 32 2


0
10 0
10

-2
a) -2
b)
10
10

Average Blocking Probability
-4
10 -4
10
N = 16

-6 N = 32
10 -6
10
N = 64
N=16 N=128
-8 -8 N=32
10 10
N=64

-10 Traffic Load = 0.9 -10
10 10
Traffic Load=0.9
-12 -12
10 10
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Internal Links

HOLB vs. number of internal links under 90% traffic load for switch sizes N=16, N=32
and N=64. a) our results. b) Santos-Motoyama results.


0 0
10 10

a) b)
-2 -2
10 10

-4 -4
10 10
Traffic Load = 0.7
Traffic Load = 0.8 ρ = 0.7 ρ = 0.9
Traffic Load = 0.9
ρ = 0.8 ρ =1
-6 Traffic Load = 1.0 -6
10 10

-8 -8
10 10

Switch Size: 64 X 64 Switch Size: 64 x 64
-10 -10
10 10
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

HOLB vs. number of internal links for a 64x64 switch under several traffic loads. a) our
results. b) Santos-Motoyama results.


1
10 1
10
N = 8 N=8
N = 16 N=16
0 N = 32 N=32
10 0
N = 64 10
N=64

-1
10 -1
10

-2
10 -2
10

-3
10 -3
10

-4
10 -4
10

-5
10 -5
2 3 4 5 6
10
2 3 4 5 6
a) b)
Mean input buffer occupation vs m under 90% traffic load for switch sizes N=8, N=16,
N=32 and N=64. a) our results. b) Santos-Motoyama results.



8 16 32 64
m
3 5 7 7 9
4 3 3 4 4
5 2 2 2 3
6 2 2 2 2

Maximum occupation for input queues under 90% traffic load.


0
10 0
10
Class 1 - 40% class1 - 40%
-1
Class 2 - 20% class2 - 20%
10 -1
Class 3 - 20% 10 class3 - 20%
Class 4 - 10% class4 - 10%
-2
Class 5 - 10% class5 - 10%
-2
10 10

Average Queue Length
-3 -3
10 10

-4 -4
10 10

-5 -5 Switch Size: 16x16
10 10

-6 -6
10 Traffic Load: 0.9
10

-7
-7 10
10
2 3 4 5 6 2 3 4 5 6
Internal Links

a) b)
Per class mean input queue occupation vs m for a 16x16 switch under 90% traffic load.
a) our results. b) Santos-Motoyama results.


1 1
10 10
Classe 1 class1
Classe 2 class2
Classe 3 class3
Classe 4 class4
Classe 5 class5

Average Queue Length
A verage Queue Length

0 0
10 10

Traffic Load: 0.9 Switch Size: 16x16
Switch Size: 16x16 Traffic Load: 0.9

-1 -1
10 10

2 3 4 5 6 2 3 4 5 6
Internal Links Internal Links

a) b)
Per class mean output queue occupation vs m for a 16x16 switch under 90% traffic load.
a) our results. b) Santos-Motoyama results.


Final Remarks
We presented modeling, simulation and performance
evaluation of two Santos-Motoyama CIOQ architectures.

We validated and compared results with SM previous work.

We proved that the studied CIOQs can reduce HOLB using a
simple solution and without high speed rates inside the
switch, producing a good improvement with regard to Input
Queueing, not only in terms of occupation reduction, but also
in terms of HOLB decrease.

Future works include performance evaluation under other
traffic patterns, traffic classes, load situations, internal links
and packet sizes (focusing on IP/MPLS/DiffServ networks).


Thank You!
alberti@inatel.br
tiao@femc.edu.br
anilton@inf.ufes.br

Apresentação feita em 2006 no Annual Simulation Symposium.

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