VHDL_Lecture_new1 [Autosaved].ppt

VHDL is an acronym for VHSlC Hardware Description Language
(VHSIC is an acronym for Very High Speed Integrated Circuits).
It is a hardware description language that can be used to model a digital
system at many levels
The complexity of the digital system being modeled could vary from that
of a simple gate to a complete digital electronic system, or anything in
between.
The VHDL language can be regarded as an integrated amalgamation of
the following languages:
sequential language + concurrent language +*net-list language +
timing specifications +waveform generation language => VHDL
*netlist is a description of the connectivity of an electronic circuit
The language has constructs that enable you to express the concurrent
or sequential behavior of a digital system with or without timing.
It also allows you to model the system as an interconnection of
components
VHDL -INTRODUCTION

HISTORY
A team of three companies, IBM, Texas Instruments, and
Intermetrics, were first awarded the contract by the DoD to develop
a version of the language in 1983. Version 7.2 of VHDL was
developed and released to the public in 1985.
After the release of version 7.2, there was an increasing need to
make the language an industry-wide standard. Consequently, the
language was transferred to the IEEE for standardization in 1986.
After a substantial enhancement to the language, made by a team
of industry,
university, and DoD representatives, the language was standardized
by the IEEE in December 1987; this version of the language is now
known as the IEEE Std 1076-1987.

Soon after IEEE 1076-1987 was adopted, simulator companies began
enhancing VHDL with new signal types to allow their customers to
accurately simulate complex electronic circuits.
This causes problems because design descriptions entered using one
simulator were often incompatible with other simulation environments.
VHDL was quickly becoming a non-standard.
To get around this problem of non-standard data types, another standard
was developed by commitee and adopted by the IEEE.
This standard, numbered 1164, defines a standard package (a VHDL
feature that allows commonly used declarations to he collected into an
external library) containing definitions for a standard nine-valued data type.
This standard data type is called standard logic, and the IEEE 1164
package is often referred to as the standard logic package, or sometimes
MVL9 (for mutivalued logic, nine values).
The IEEE 1076-1987 and IEEE 1164 standards together form the complete
VHDL standard in widest use today.

VHDL-BASICS
VHDL provides five different types of primary constructs, called"
design units.
They are
1. Entity declaration
2. Architecture body
3. Configuration declaration
4. Package declaration
5. Package body
The entity declaration describes the external view of the
entity, for example, the input and output signal names.
The architecture body contains the internal description of
the entity.
For example, as a set of interconnected components that
represents the structure of the entity, or as a set of
concurrent or sequential statements that represents the
behavior of the entity.

BASICS
Lexical ELEMENTS OF VHDL
VHDL is case insensitive language i.e. upper and lower case
letters have same meanings.
Further, 1-bit numbers are written in single quotation mark and
numbers with more than 1-bit are written in double quotation mark,
e.g. ‘0’ and ‘‘01’’ are the valid notations.
Also, VHDL is free formatting language (i.e. spaces can be added
freely.

Comments in a description must be preceded by two
consecutive hyphens (-); the comment extends to the
end of
the line. Comments can appear anywhere within a
description. Examples are
--This is a comment; it ends at the end of this line.
--To continue a comment onto a second line, a
separate
-- comment line must be started.
Basics

BASICS
LEXICAL ELEMENTS OF VHDL
Identifiers are user-defined words used to name objects in VHDL
models.
•May contain only alpha-numeric characters (A to Z, a to z, 0-9) and
the underscore (_) character
•The first character must be a letter and the last one cannot be an
underscore.
•An identifier cannot include two consecutive underscores.
•An identifier is case insensitive (ex. And2 and AND2 or and2 refer to
the same object)
•An identifier can be of any length.
Examples of valid identifiers are: X10, x_10, My_gate1.
Decoder_1 FFT Sig_N Not_Ack
Some invalid identifiers are: _X10, my_gate@input, gate-
input.
_Decoder_1 2FFT Sig_#N

BASICS-LEXICAL ELEMENTS
The above identifiers are called basic identifiers. The rules for these basic
identifiers are often too restrictive to indicate signals. For example, if one
wants to indicate an active low signal such as an active low RESET, one
cannot call it /RESET. In order to overcome these limitations, there are a set
of extended identifier rules which allow identifiers with any sequence of
characters.
The extended identifiers are braced between two backslash characters.
They may contain any graphic character (including spaces and non-
ASCII characters), as well as reserved words.
If a backslash is to be used as one of the graphic characters of an
extended literal, it must be doubled
An extended identifier is case sensitive.
An extended identifier is different from reserved words (keywords) or
any basic identifier

BASICS
Inside the two backslashes one can use any
character in any order, except that a backslash as
part of an extended identifier must be indicated by
an additional backslash.
As an example, to use the identifier BUS:data, one
writes: BUS:dataExtended identifiers are allowed
in the VHDL-93 version but not in VHDL-87
EX:
signal C:Cads Signal @#

BASICS
1.Numbers
The default number representation is the decimal system. VHDL allows
integer literals and real literals. Integer literals consist of whole numbers
without a decimal point, while real literals always include a decimal point.
Exponential notation is allowed using the letter “E” or “e”. For integer
literals the exponent must always be positive. Examples are:
Integer literals: 12 10 256E3 12e+6
Real literals: 1.2 256.24 3.14E-2
The number –12 is a combination of a negation operator and an integer
literal.

Data Objects
A data object holds a value of a specified type. It is created by means of an
object declaration. An example is
Every data object belongs to one of the following three classes: Constants,
Variables, Signal and Files.
1. Constant: An object of constant class can hold a single value of a
given type. This value is assigned to the object before simulation starts
and the value cannot be changed during the course of the simulation.
2. Variable: An object of variable class can also hold a single value of
a given type. However in this case, different values can be assigned
to the object at different times using a variable
assignment statement.
3. Signal: An object belonging to the signal class has a past history
of values, a current value, and a set of future values. Future values
can be assigned to a signal object using a signal
assignment statement.
4. File Data objetcs are used exclusively in simulations

Constant Declarations
Examples of constant declarations are
constant RISE_TIME: TIME := 10ns;
constant BUS_WIDTH: INTEGER := 8:
The first declaration declares the object RISE_TIME that can hold a value
of type TIME (a predefined type in the language) and the value assigned
to the object at the start of simulation is 10 ns. The second constant
declaration declares a constant BUS_WIDTH of type INTEGER with a
value of 8.

Variable Declarations Examples of variable declarations are
variable CTRL_STATUS: BIT_VECTOR(10 downto 0);
variable SUM: INTEGER range 0 to 100 := 10;
Signal Declarations
Here are some examples of signal declarations.
signal CLOCK: BIT;
signal DATA_BUS: BIT_VECTOR(0 to 7);
signal GATE_DELAY: TIME := 10 ns;

BASICS
To express a number in a base different from the base “10”, one uses the
following convention: base#number#. A few examples follow.
Base 2: 2#10010# (representing the decimal number “18”)
Base 16: 16#12#
Base 8: 8#22#
Base 2: 2#11101# (representing the decimal number “29”)
Base 16: 16#1D#
Base 8: 8#35#
To make the readability of large numbers easier, one can insert
underscores in the numbers as long as the underscore is not used at the
beginning or the end.
2#1001_1101_1100_0010#
215_123

BASICS
1.Characters, Strings and Bit Strings
To use a character literal in a VHDL code, one puts it in a single
quotation mark, as shown in the examples below:
‘a’, ‘B’, ‘,’
On the other hand, a string of characters are placed in double quotation
marks as shown in the following examples:
“This is a string”,
“To use a double quotation mark inside a string, use two double
quotation marks”
“This is a “”String””.”
Any printing character can be included inside a string.

BASICS
A bit-string represents a sequence of bit values. In order to indicate
that this is a bit string, one places the ‘B’ in front of the string:
B”1001”. One can also use strings in the hexagonal or octal base by
using the X or O specifiers, respectively. Some examples are:
Binary: B”1100_1001”, b”1001011”
Hexadecimal: X”C9”, X”4b”
Octal: O”311”, o”113”
Notice that in the hexadecimal system, each digit represents exactly
4 bits. As a result, the number b”1001011” is not the same as X”4b”
since the former has only 7 bits while the latter represents a
sequence 8 bits. For the same reason, O”113” (represents 9 bits) is
not the same sequence as X”4b” (represents 8 bits).

BASICS
Library and packages
In general we use only two packages i.e. ‘std_logic_1164’ and
‘numeric_std’ packages, which are approved by IEEE. Further, There are
various other non-IEEE-standard packages available e.g. std_logic_arith’
etc., which allow quick and easy coding with VHDL. Since these are not
standardized library therefore it may result in compatibility issues.
std_logic_1164’ package
The ‘std_logic_1164’ package contains the various data types e.g.
‘std_logic’, ‘std_logic_vector’ and ‘integer’ etc. But we can not control the
size of the integer (default 32 bit size) and format (i.e. sign and unsigned)
using this package. Further, ‘Natural’ data type is available in this
package, which allows only ‘0’ and positive integer values.

BASICS
‘numeric_std’ package
We can not perform various mathematical operations on the data
type which are defined in ‘std_logic_1164’ package. To perform
various mathematical operations and to gain more control over
integer values, ‘numeric_std’ package can be used. This package
allows ‘sign’ and ‘unsigned’ integer values along with the size control.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

BASICS
‘textio’ and ‘std_logic_textio’ packages
These packages are used in testbences to write and read the data
to the file.
Other standard packages
There are some more standard packages like ‘numeric_bit’,
‘standard’,’numeric_bit_unsigned’ and ‘numeric_std_unsigned’.
Further, there are various standard packages are available for
‘fixed point’ and ‘floating point’ operations as well e.g.’fixed_pkg’,
‘float_pkg’, ‘fixed_float_types’, ‘fixed_generic_pkg’ and
‘float_generic_pkg’.

BASICS
Notice that the nand and nor operators are not associative. One
should use parentheses in a sequence of nand or
nor operators to prevent a syntax error:
X nand Y nand Z will give a syntax error and should be written as (X nand Y) nand Z.

BASICS
The relational operators test the relative values of two scalar types
and give as result a Boolean output of
“TRUE” or “FALSE”.

Addition operators
The addition operators are used to perform arithmetic operation (addition and subtraction) on
operands of any numeric type. The concatenation (&) operator is used to concatenate two
vectors together to make a longer one.
In order to use these operators one has to specify the ieee.std_logic_unsigned.all or
std_logic_arith package package in addition to the ieee.std_logic_1164 package

These operators perform a bitwise shift or rotate operation on a
onedimensional array of elements of the type bit (or std_logic) or
Boolean

The operand is on the left of the operator and the number
(integer) of shifts is on the right side of the operator.
As an example,
variable NUM1 :bit_vector := “10010110”;
NUM1 srl 2;
will result in the number “00100101”.
When a negative integer is given, the opposite action occurs, i.e.
a shift to the left will be a shift to the right. As an
example
NUM1 srl –2 would be equivalent to NUM1 sll 2 and give the
result “01011000”.

BASICS
• Every VHDL design description consists of at least one entity /
architecture pair, or one entity with multiple architectures.
• The entity section is used to declare I/O ports of the circuit. The
architecture portion describes the circuit’s behavior

VHDL – BASIC LANGUAGE
ELEMENTS
•PORT declaration establishes the interface of the
object to the outside world.
•Three parts of the PORT declaration
• Name
• Any identifier that is not a reserved word.
• Mode
• In, Out, Inout, Buffer
• Data type
• Any declared or predefined datatype.
•Sample PORT declaration syntax:

Entity Declaration
The entity declaration defines the NAME of the entity and lists
the input and output ports. The general form is as follows,

An entity always starts with the keyword entity, followed by
its name and the keyword is. Next are the port declarations
using the keyword port. An entity declaration always ends with
the keyword end, optionally [] followed by the name of the
entity.
generic: generic declarations are optional and determine the local
constants used for timing and sizing (e.g. bus widths) the entity. A generic
can have a default value. The syntax for a generic follows,
generic ( constant_name: type [:=value] ; constant_name: type
[:=value]) ;
generic (DELAY: time :=5ns)

ENTITY DECLARATION FOR
AND GATE
entity AND_GATE is
Port ( A, B: in BIT; Z : out BIT);
end AND_GATE;

ENTITY DECLARATION FOR HALF
ADDER

ENTITY DECLARATION OF
FULL ADDER
entity full_adder is
Port ( A, B,C_in : in STD_LOGIC;
sum, C_out: out STD_LOGIC );
end full_adder;
sum= (A xor B) xor C_in
C_out=((A xor B) and C_in) or (A and
B)

ENTITY DECLARATION FOR 1 BIT
COMPARATOR
entity onebitcomp is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
EQ: out STD_LOGIC;
GT: out STD_LOGIC;
LT: out STD_LOGIC );
end onebitcomp;
GT
EQ
LT

ENTITY DECLARATION FOR 4X1 MULTIPLEXER
entity fouronemux is
Port ( s: in STD_LOGIC_VECTOR (1
downto 0);
I : in STD_LOGIC_VECTOR (3 downto
0);
Y : out STD_LOGIC);
end fouronemux;

TWO BIT COMPARATOR
LT
EQ
GT
entity twobitcomp is
port ( A0,A1,B0,B1: in STD_LOGIC;
LT,EQ,GT : out STD_LOGIC);
end twobitcomp;

Architecture body
The architecture body specifies how the circuit operates and how it is
implemented. As discussed earlier, an entity or circuit can be specified in a
variety of ways, such as behavioral, structural (interconnected components),
or a combination of the above.
The architecture body looks as follows,
architecture architecture_name of NAME_OF_ENTITY is
--Declarations
--Components declarations
--Signal declarations
--Constant declarations
--Function declarations
--procedure declarations
--type declarations
:
begin
--Statements
:
end architecture_name;

FULL ADDER
entity full_adder is
Port ( A, B,C_in : in STD_LOGIC;
sum, C_out: out STD_LOGIC );
end full_adder;
architecture behavioral of full_adder is
begin
Sum<= (A xor B) xor C_in;
C_out<=((A xor B) and C_in) or (A and B);
End behavioral;
sum= (A xor B) xor C_in
C_out=((A xor B) and C_in) or (A and
B)

ARCHITECTURE BODY OF
AND GATE
architecture Behavioral of AND_GATE is
begin
Z<=A AND B;
end Behavioral;

ARHITECTURE BODY OF HALF
ADDER
architecture Behavioral of HALF_ADDER
is
begin
SUM<=A XOR B;
CARRY<=A AND B;
end Behavioral;

FULL ADDER
architecture behavioral of full_adder is
begin
Sum<= (A xor B) xor C_in;
C_out<=((A xor B) and C_in) or (A and B);
end behavioral;

ARCHITECTURE BODY OF ONE BIT
COMPARATOR
architecture Behavioral of onebitcomp is
begin
GT<=AAND (NOT B);
EQ<=A XNOR B;
LT<= (NOT A) AND B;
end Behavioral;
GT
EQ
LT

4X1 MUXS(1) S(0)
I(0)
I(1)
I(2)
I(3)

ARCHITECTURE BODY OF 4X1
MUX
architecture Behavioral of fouronemux is
begin
Y<=(I(0) and not s(1) and not s(0)) or (I(1) and not s(1) and
s(0)) or (I(2) and s(1) and not s(0)) or (I(3) and s(1) and
s(0));
end Behavioral;

ARCHITECTURE BODY OF
TWO BIT COMPARATOR
LT<=(not A1 and B1) or(not A0 and B1 and B0) or ( not A1 and not A0 and B0);
EQ<=(A1 xnor B1) and (A0 xnor B0);
GT<=( A1 and not B1) or( A0 and not B1 and not B0) or ( A1 and A0 and not B0)
architecture Behavioral of twobitcomp is
begin
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HALF_ADDER is
Port ( A : in BIT; B : in BIT; SUM : out BIT; CARRY :
out BIT);
end HALF_ADDER;
architecture Behavioral of HALF_ADDER is
begin
SUM<=A XOR B;
CARRY<=A AND B;
end Behavioral;

DATA FLOW MODELING
In this modeling the flow of data through the entity is expressed
using concurrent assignment statements.
The dataflow model of the half adder is described using two
concurrent signal assignment statements.
begin
SUM<=A XOR B;
CARRY<=A AND B;
end Behavioral;
In a signal assignment statement, the symbol <= implies an
assignment of a value to a signal.
The value of the expression on the right hand side of the
statement is computed and is assigned to the signal on the left-
side.
A concurrent signal assignment statement is executed only when
any signal used in the expression on the right hand side has an
event on it, that is the value of the signal changes.

DATAFLOW MODELING
DELAY INFORMATION ALSO CAN BE INCLUDED IN THE
CONCURRENT STATEMENTS
begin
SUM<=A XOR B after 8 ns;
CARRY<=A AND B after 4 ns;
end Behavioral;

DATAFLOW MODELING
entity DECODER2X4_DF is
Port ( S: in STD_LOGIC_VECTOR(1 downto 0) ; EN: in
STD_LOGIC;
Y : out STD_LOGIC_VECTOR (3 downto 0));
end DECODER2X4 ;
architecture behavioral of DECODER2X4_DF is
signal S0bar, S1bar: STD_LOGIC;
begin
Y(3)<= S(0) and S(1) and EN; --
statement 1
Y(0)<= S0bar and S1bar and EN; --
statement 2
S1bar<=not S(1); -- statement 3
Y(2)<= S(1) and S0bar and EN; -- statement
4
S0bar<=not S(0); -- statement 5
Y(1)<=S1bar and S(0) and EN; -- statement

STRUCTURAL MODELING
The architecture body of structural modelling consists of
two parts
 Component declaration
 Signal declaration
 Component Instantiation
In Component declaration the name and interface of the component is
declared
component component_name is
[port (list-of-interface-ports);]
end component;
The component name may or maynot refer to the name of an entity
already existing in a library. If it does not, it must be explicitly bound
to entity.
The list-of-interface-ports specifies the name , mode and type of each
port of the component in a manner similar to that specified in an entity
declaration

ECE C03 LECTURE 17ECE C03 LECTURE 6 70
COMPONENT AND SIGNAL
DECLARATIONS
Example of component declaration
 component OR_GATE is
port (A, B: in bit; Z : out bit);
 end component;
Ex:
 Component AND_GATE is
port(A, B: in STD_LOGIC; z: out STD_LOGIC);
end component;
Signals are needed to interconnect components
 signal INT1, INT2, INT3: bit;

A component instantiation statement defines a subcomponent of the entity in
which it appears. It associates the signals in the entity with the ports of that
subcomponent. A format of a component instantiation statement is
component-label: component-name port map ( association-
list) ;
The component-label can be any legal identifier and can be considered as the
name of the instance.
The component-name must be the name of a component declared earlier using
a component declaration.
The association-list associates signals in the entity, called actuals, with the ports
of a component, called locals
Component Instantiation Statements

There are two ways to perform the association of locals with actuals:
1. positional association, 2. named association.
In positional association, an association-list is of the form actual1,
actual2, actual3, . . ., actualn
Each actual in the component instantiation is mapped by position
with each port in the component declaration.
Component Instantiation Statements

That is, the first port in the component declaration corresponds to
the first actual in the component instantiation, the second with the
second, and so on. Consider an instance of a NAND2 component
. -- Component declaration:
component NAND2
port (A, B: in BIT; Z: out BIT);
end component;
-- Component instantiation:
N1: NAND2 port map (S1, S2, S3);

In named association, an association-list is of the form
local1 => actual1, local2 => actual2, ..., localn => actualn
component NAND2
port (A, B: in BIT; Z: out BIT);
end component;
-- Component instantiation:
N1: NAND2 port map (A=>S1, B=>S2, Z=>S3);

ECE C03 LECTURE 17ECE C03 LECTURE 6 75
COMPONENT INSTANTIATION
STATEMENTS
The statement part of an architecture body of a
structural VHDL description contains component
instantiation statements
FORMAT
label : component_name port map (positional association of ports);
label : component_name port map (named association of ports);
EXAMPLES
A1: AND2_OP port map (A_IN, B_IN, INT1);
A2: AND2_OP port map (A=>A_IN, C=>C_IN,Z=>INT2);

VHDL PROGRAM FOR AND GATE
Component declaration for AND_GATE is
Component AND_GATE is
port(l, m: in STD_LOGIC; n: out
STD_LOGIC);
end component;
library IEEE;
entity AND_GATE is
port ( l ,m : in STD_LOGIC; n :
out STD_LOGIC);
end AND_GATE;
architecture behavioral of
AND_GATE is
begin
n<= l AND m;
end behavioral;

VHDL PROGRAM FOR XOR GATE
library IEEE;
entity XOR_GATE is
Port ( e ,f : in STD_LOGIC; g : out
STD_LOGIC);
end XOR_GATE;
architecture Behavioral of XOR_GATE is
begin
g<=e xor f;
end Behavioral;
Component declaration for XOR GATE
is
Component XOR_GATE is
Port ( e ,f : in STD_LOGIC; g : out
STD_LOGIC);
end component;

VHDL PROGRAM FOR OR
GATE
library IEEE;
entity OR_GATE is
Port ( p ,q : in STD_LOGIC; r : out
STD_LOGIC);
end XOR_GATE;
architecture Behavioral of XOR_GATE is
begin
r<=p or q;
end Behavioral;
Component declaration for OR GATE is
Component OR_GATE is
Port ( p ,q : in STD_LOGIC; r : out
STD_LOGIC);
end component;

STRUCTURAL MODELLING FOR
HALF ADDER
library IEEE;
entity HA is
Port ( A,B : in STD_LOGIC; S,C:out STD_LOGIC);
end HA;
architecture HA_ST of HA is
-- component declaration
Component AND_GATE is
port(l, m: in STD_LOGIC; n: out STD_LOGIC);
end component;
Component XOR_GATE is
port ( e ,f : in STD_LOGIC; g : out STD_LOGIC);
end component;
-- signal declaration
-- Component Instantiation
begin
X: XOR_GATE port map(A,B,S);
A: AND_GATE port map(A,B,C);
end HA_ST;

STRUCTURAL MODELLING FOR FULL ADDER
library IEEE;
entity FA is
port ( A_1, B_1,C_in : in STD_LOGIC; SUM,CARRY: out STD_LOGIC);
end FA;
architecture FA_ST of FA is
-- component declaration
component HA is
port ( A,B : in STD_LOGIC; S, C:out STD_LOGIC);
end component;
component OR_GATE is
port ( p ,q: in STD_LOGIC; r : out STD_LOGIC);
end component;
signal s1,c1,c2:STD_LOGIC;
-- Component Instantiation
begin
HA1: HA port map(A_1,B_1,s1,c1);
HA2: HA port map(s1,C_in,SUM,c2)
OR1: OR_GATE port map(c2,c1,CARRY);
end FA_ST;

Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity fourbitRCA is
port ( x: in STD_LOGIC_VECTOR (3 downto 0);
y: in STD_LOGIC_VECTOR (3 downto 0);
cy : out STD_LOGIC; z:out STD_LOGIC_VECTOR(3 downto 0));
end fourbitRCA;
--Component declaration
architecture RCA_ST of fourbitRCA is
component FA is
port ( A_1, B_1,C_in : in STD_LOGIC; SUM,CARRY: out STD_LOGIC);
end component;
signal cy0,cy1,cy2: STD_LOGIC;
-- component Instantiation
FA0: FA port map(x(0),y(0),’0’,z(0),cy0);
FA1: FA port map(x(1),y(1),cy0,z(1),cy1);
FA2: FA port map(x(2),y(2),cy1,z(2),cy2);
FA3: FA port map(x(3),y(3),cy2,z(3),cy);
end RCA_ST;

STRUCTURAL MODELLING OF 2X4 DECODER

It is combinational circuit that accepts an n-1 bit stream data and
generates the additional bit that is to be transmitted with the bit stream.
This additional or extra bit is termed as a parity bit. In even parity bit
scheme, the parity bit is ‘0’ if there are even number of 1s in the data
stream and the parity bit is ‘1’ if there are odd number of 1s in the data
stream. In odd parity bit scheme, the parity bit is ‘1’ if there are even
number of 1s in the data stream and the parity bit is ‘0’ if there are odd
number of 1s in the data stream. Let us discuss both even and odd parity
generators.

ELEMENTS
Identifiers:
 basic identifier: composed of a sequence of one or more
characters
 upper case, lower case, digit, underscore
 first character must be a letter, last character must NOT be
an underscore
 Two underscores cannot occur concurrently
 case insensitive: COUNT, count, Count, counT are all the
same
 extended identifier: sequence of characters written between two
backslashes
 Any printable characters can be used including %, $, *, etc.
 lower case and upper case are distinct
 examples: 2FOR$, countNow!, &#$(@#&!!!
 Keywords can not be used as basic identifiers

ELEMENTS
Data Objects – hold a value of a specified type
 constant: holds a single value of a specified type and
cannot be changed throughout the simulation
 constant declaration:
 constant RESULT: BIT:=1; constant FALL_TIME:
TIME:=10ns
 variable: holds a single value of a specified type but can
be changed throughout the simulation
 variable ABAR:BIT; variable STATUS:BIT_VECTOR(3
down to 0);
 signal: holds a list of values including current value and
a list of possible future values
 typically used to model wires and flip-flops
 signal DATA_BUS:BIT_VECTOR(0 to 31)
 file: same as with any computer file, contains data

ELEMENTS
Include library ieee; before entity declaration.
ieee.std_logic_1164 defines a standard for
designers to use in describing interconnection
data types used in VHDL modeling.
ieee.std_logic_arith provides a set of
arithmetic, conversion, comparison functions
for signed, unsigned, std_ulogic, std_logic,
std_logic_vector.
Ieee.std_logic_unsigned provides a set of
unsigned arithmetic, conversion, and
comparison functions for std_logic_vector.

ELEMENTS
Data Types – specifies the constraints on values held by an object and the
kind of value it is
There are pre-defined types such as:
 INTEGER (231 –1 to –231)
 BOOLEAN (true, false)
 BIT (0, 1)
There can also be user-defined types and subtypes
There are several categories of types including scalar, composite, access, and
file types
 We’ll focus on the scalar and composite
A subtype is a type with a (possibly) added constraint
 subtype SPC_INTEGER is INTEGER range 5 to 15;
 subtype HALF_BIT is BIT range 0 to 0;
 subtype NUMBER is INTEGER; -- no extra constraints here
subtype MY_INTEGER is INTEGER range 48 to 156 ;
type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ;
subtype MIDDLE is DIGIT range '3' to '7' ;

ELEMENTS
Scalar types: There are four different kinds of data
Types
 Enumeration – defines a type that has a set of
user-defined values
 type MY_VAL is (‘0’, ‘1’, ‘2’, ‘3’);
 type LOGIC is (AND, OR, NOT, XOR);
 Example declaration: variable AIN:LOGIC;
 Integer – values fall within the specified integer
range
 type REG_SIZE is range 0 to 31
 subtype WORD is REG_SIZE range 0 to 15
 Floating Point – decimal types: Examples of floating
point type declarations are : type TTL_VOLTAGE is range -5.5
to -1.4;
 type REAL_DATA is range 0.0 to 31.9;

ELEMENTS
Floating -point literals are values of a floating point type.
Examples of floating point literals are
16.26 0.0 0.002 3_1.4_2
Floating point literals can also be expressed in an
exponential form. The exponent represents a power of
ten and the exponent value must be an integer.
Examples are
62.3 E-2 5.0 E+2
Integer and floating point literals can also be written in a
base other than 10 (decimal). The base can be any value
between 2 and 16. Such literals are called based literals

ELEMENTS
The syntax for a based literal is
base # based-value # -- form 1
base # based-value # E exponent -- form 2
Examples are
2#101_101_000# represents (101101000)2 = (360) in
decimal,
16#FA# represents (FA)16= (11111010)2 = (250) in
decimal,
16#E#E1 represents (E)16* (16^1) = 14* 16= (224) in
decimal,
2#110.01 # represents (110.01)2 = (6.25) in decimal.

ELEMENTS
Physical Types
A physical type contains values that represent
measurement of some physical quantity, like time,
length, voltage, and current. Values of this type are
expressed as integer multiples of a base unit. An
example of a physical type declaration is
type CURRENT is range 0 to 1 E9
 units
nA; -- (base unit) nano-ampere
uA = 1000 nA; -- micro-ampere
mA = 1000 μA; --milli-ampere
Amp = 1000 mA; -- ampere
 end units;
subtype FILTER_CURRENT is CURRENT range 10 μA to 5
mA;

ELEMENTS
Composite Types – a collection of values
 Array Types – collection of values all belonging to a
single type
 BIT_VECTOR and STRING are pre-defined one-
dimensional array types
 type DATA_BYTE is array (0 to 7) of BIT;
 type MEMORY is array (0 to 127) of DATA_BYTE;
Examples of object declarations using these types are
variable ROM_ADDR: ROM;
signal ADDRESS.BUS: ADDRESS_WORD;
constant DECODER: DECODE_MATRIX; - A deferred
constant.
variable DECODE_VALUE: DECODE_MATRIX;

ELEMENTS
 Record Types – collection of values that may belong to
different types
 Similar to a “struct” declaration in C
type MODULE is
record
SUM:BIT_VECTOR(0 to 7);
COUT:BIT;
end record

ELEMENTS
Access Types
Values belonging to an access type are pointers to a
dynamically allocated object of some other type. They
are similar to pointers in Pascal and C languages.
Examples of access type declarations are
-- MODULE is a record type declared in the previous
sub-section.
type PTR is access MODULE;
type FIFO is array (0 to 63, 0 to 7) of BIT;
type FIFO_PTR is access FIFO;

ELEMENTS
Incomplete Types
It is possible to have an access type that points to an
object that has elements which are also access types.
This can lead to mutually dependent or recursive access
types. Since a type must be declared before it is used, an
incomplete type declaration can be used to solve this
problem. An incomplete type declaration has the form
type type-name;
Once an incomplete type has been declared, the type-name can now be
used in any mutually dependent or recursive access type. However, a
corresponding full type declaration must follow later. An example of a
mutually dependent access type is
type COMP; -- Record contains component name and list of
 -- nets its connected to.
type NET; -- Record contains net name and list of
-- components it is connected to.

ELEMENTS
File Types
Objects of file types represent files in the host
environment. They provide a mechanism by which a
VHDL design communicates with the host environment.
The syntax of a file type declaration is
type file-type-name Is file of type-name,
The type-name is the type of values contained in the file.
Here are two examples.
type VECTORS is file of BIT_VECTOR;
type NAMES is file of STRING;
A file of type VECTORS has a sequence of values of type
BIT_VECTOR; a file of type NAMES has a sequence of
strings as values in it.
A file is declared using a file declaration.The syntax of a
file declaration is:

ELEMENTS
file file-name: file-type-name is mode string-expression
',
The string-expression is interpreted by the host
environment as the physical name of the file. The mode
of a file, in or out, specifies whether it is an input or an
output file, respectively. Input files can only be read
while output files can only be written to.
Here are two examples of declaring files.
file VEC_FILE: VECTORS is in
"/usr/home/jb/uart/div.vec";
file OUTPUT: NAMES is out "stdout";

ELEMENTS
Operators
 logical operators
 and, or, nand, nor, xor, xnor, not
 relational operators
 <, >, =, <=, >=, /= -- /= means not equal to
 shift operators
 logical shift left, logical shift right, arithmetic shift left, arithmetic shift right,
rotate left, rotate right
 sll, srl, sla, sra, rol, ror
 adding operators
 +, -, & -- & is concatenation
 multiplying operators
 *, /, mod, rem
 miscellaneous operators
 abs, ** -- ** is exponentiation

ELEMENTS
•An entity declaration describes the interface of the
component. Avoid using Altera’s primitive names which
can be found at
c:/altera/91/quartus/common/help/webhelp/mast
er.htm#
•PORT clause indicates input and output ports.
•An entity can be thought of as a symbol for a
component.

ELEMENTS
•Architecture declarations describe the operation of the
component.
•Many architectures may exist for one entity, but only one
may be active at a time.
•An architecture is similar to a schematic of the
component

ELEMENTS
•There are three modeling styles:
•Data flow
•Structural
•Behavioral (Sequential)

DATAFLOW MODELING
A dataflow model specifies the functionality of the entity
without explicitly specifying its structure.
This functionality shows the flow of information through
the entity, which is expressed primarily using concurrent
signal assignment statements and block statements.
This is in contrast to the behavioral style of modeling , in
which the functionality of the entity is expressed using
procedural type statements that are executed
sequentially.

DATAFLOW MODELING
Concurrent Signal Assignment Statement : One of the
primary mechanisms for modeling the dataflow behavior
of an entity is by using the concurrent signal assignment
statement.
entity OR2 is
port (signal A, B: in BIT; signal Z: out BIT);
end OR2;
architecture OR2 of OR2 is
begin
 Z <= A or B after 9 ns;
end OR2;

DATAFLOW MODELING
architecture HA_CONCURRENTof HALF_ADDER is
begin
SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns;
end HA_CONCURRENT;

The dataflow model for the HALF_ADDER is described using two
concurrent signal assignment statements. In a signal assignment statement,
the symbol <= implies an assignment of a value to a signal. The value of the
expression on the right-hand-side of the statement is computed and is
assigned to the signal on the left-hand-side, called the target signal. A
concurrent signal assignment statement is executed only when any signal
used in the expression on the right-hand-side has an event on it, that is, the
value for the signal changes.
Delay information is included in the signal assignment statements using after
clauses. If either signal A or B, which are input port signals of
HALF_ADDER entity, has an event, say at time T, the right-hand-side
expressions of both signal assignment statements are evaluated. Signal SUM
is scheduled to get the new value after 8 ns while signal CARRY is
scheduled to get the new value after 4 ns. When simulation time advances to
(T+4) ns, CARRY will get its new value and when simulation time advances
to (T+8) ns, SUM will get its new value. Thus, both signal assignment
statements execute concurrently.

DATAFLOW MODELING
An architecture body can contain any number of
concurrent signal assignment statements. Since they are
concurrent statements, the ordering of the statements is
not important. Concurrent signal assignment statements
are executed whenever events occur on signals that are
used in their expressions.
entity FULL_ADDER is
port (A, B, CIN: in BIT; SUM, COUT: out BIT);
end FULL_ADDER;
architecture FULL_ADDER of FULL_ADDER is
begin
SUM <= (A xor B) xor CIN after 15 ns;
COUT <= (A and B) or (B and CIN) or (CIN and A) after 10
ns;

DATAFLOW MODELING
Here is a dataflow model for the DECODER2x4 entity.
architecture dec_dataflgw of DECODER2x4 is
signal ABAR, BBAR: BIT;
begin
Z(3) <= not (A and B and ENABLE); - statement 1
Z(0) <= not (ABAR and BBAR and ENABLE); - statement 2
BBAR <= not B; - statement 3
Z(2) <= not (A and BBAR and ENABLE); - statement 4
ABAR <= not A; - statement 5
Z(1 ) <= not (ABAR and B and ENABLE); - statement 6
end DEC_DATAFLOW;

The architecture body consists of one signal declaration and six
concurrent signal assignment statements. The signal declaration
declares signals ABAR and BBAR to be used locally within the
architecture body. In each of the signal assignment statements, no
after clause was used to specify delay. In all such cases, a default
delay of 0ns is assumed. This delay of 0ns is also known as delta
delay, and it represents an infinitesimally small delay. This small
delay corresponds to a zero delay with respect to simulation time
and does not correspond to any real simulation time

To understand the behavior of this architecture body, consider an
event happening on one of the input signals, say input port B at time
T. This would cause the concurrent signal assignment statements
1,3, and 6, to be triggered. Their right-hand-side expressions would
be evaluated and the corresponding values would be scheduled to
be assigned to the target signals at time (T+Δ). When simulation
time advances to (T+ Δ), new values to signals Z(3), BBAR, and
Z(1), are assigned. Since the value of BBAR changes, this will in
turn trigger signal assignment statements, 2 and 4. Eventually, at
time (T+2 Δ), signals Z(0) and Z(2) will be assigned their new
values.
The semantics of this concurrent behavior indicate that the
simulation, as defined by the language, is event-triggered and that
simulation time advances to the next time unit when an event is
scheduled to occur. Simulation time could also advance a multiple
of delta time units.

Conditional Signal Assignment Statement
The conditional signal assignment statement selects different values for the
target signal based on the specified, possibly different, conditions (it is like
an if statement). A typical syntax for this statement is
Target - signal <= [ waveform-elements when condition else ]
[ waveform-elements when condition else ]
. . .
waveform-elements;

The semantics of this concurrent statement are as follows. Whenever an
event occurs on a signal used either in any of the waveform expressions
(recall that a waveform expression is the value expression in a waveform
element) or in any of the conditions, the conditional signal assignment
statement is executed by evaluating the conditions one at a time. For the
first true condition found, the corresponding value (or values) of the
waveform is scheduled to be assigned to the target signal. For example,
Z <= IN0 after 10ns when S0 = '0' and S1 = '0' else
IN1 after 10ns when S0 = '1' and S1 = '0' else
IN2 after 10ns when S0 = '0' and S1 = '1' else
IN3 after 10 ns;
In this example, the statement is executed any time an event occurs on
signals IN0, IN1, IN2, IN3, S0, or S1. The first condition (S0='0' and
S1='0') is checked; if false, the second condition (S0='1' and S1='0') is
checked; if false, the third condition is checked; and so on. Assuming
S0='0' and S1='1', then the value of IN2 is scheduled to be assigned to
signal Z after 10 ns.

Priority Encoder using Conditional Signal
Assignment

Selected Signal Assignment Statement
The selected signal assignment statement selects different values for a target
signal based on the,value of a select expression (it is like a case statement).
A typical syntax for this statement is
with expression select —This is the select expression.
target-signal <= waveform-elements when choices,
waveform-elements when choices,
…
waveform-elements when choices ;
The semantics of a selected signal assignment statement are very similar to
that of the conditional signal assignment statement. Whenever an event
occurs on a signal in the select expression or on any signal used in any of the
waveform expressions, the statement is executed. Based on the value of the
select expression that matches the choice value specified, the value (or
values) of the corresponding waveform is scheduled to be assigned to the
target signal.

Here is an example of a selected signal assignment statement.
type OP is (ADD, SUB, MUL, DIV);
signal OP_CODE: OP;
. . .
with OP_CODE select
Z <= A+B after ADD_PROP_DLY when ADD,
A - B after SUB_PROP_DLY when SUB,
A * B after MUL_PROP_DLY when MUL,
A / B after DIV_PROP_DLY when DIV;

4X1 mux using Selected Signal Assignment

2x4 decoder using enable and
Selected Signal Assignment

Behavioral Style of Modeling
In contrast to the styles of modeling described earlier, the behavioral style of modeling
specifies the behavior of an entity as a set of statements that are executed sequentially in
the specified order. This set of sequential statements, that are specified inside a process
statement, do not explicitly specify the structure of the entity but merely specifies its
functionality. A process statement is a concurrent statement that can appear within an
architecture body. For example, consider the following behavioral model for the
DECODER2x4 entity.
architecture DEC_SEQUENTIAL of DECODER2x4 is
begin
process (A, B, ENABLE)
variable ABAR, BBAR: BIT; begin
ABAR := not A; - statement 1
BBAR := not B; - statement 2
if (ENABLE = '1') then
--statements
Z(3) <= not (A and B): - -statement 4
Z(0) <= not (ABAR and BBAR); --statement 5
Z(2) <= not (A and BBAR); -- statement 6
Z(1 ) <= not (ABAR and B); - -statement 7
else
Z<= "1111"; --statements
end if;
end process;
end;

A process statement, too, has a declarative part (between the
keywords process and begin), and a statement part (between the
keywords begin and end process). The statements appearing
within the statement part are sequential statements and are
executed sequentially. The list of signals specified within the
parenthesis after the keyword process constitutes a sensitivity list
and the process statement is invoked whenever there is an event
on any signal in this list. In the previous example, when an event
occurs on signals A, B, or ENABLE, the statements appearing
within the process statement are executed sequentially.
The variable declaration (starts with the keyword variable)
declares two variables called ABAR and BBAR. A variable is
different from a signal in that it is always assigned a value
instantaneously and the assignment operator used is the :=
compound symbol; contrast this with a signal that is assigned a
value always after a certain delay (user-specified or the
default delta delay), and the assignment operator
used to assign a value to a signal is the <= compound
symbol.

DATAFLOW MODELING
Concurrent versus Sequential Signal Assignment
architecture SEQ_SIG_ASG of FRAGMENT1 is
- A, B and Z are signals.
begin
process (B)
begin -- Following are sequential signal assignment statements:
 A<=B;
 Z<=A;
end process;
end;
architecture CON_SIG_ASG of FRAGMENT2 is
Begin
-- Following are concurrent signal assignment statements:
A<=B;
Z<=A;
end;

Process statement
„Basic unit of Behavioral Description, found in
architectures and occasionally entities.
Entities can only contain passive process
(processes that do not make assignment to
signals)
„Process statements as a whole are
concurrent statements.
Concurrent signal assignment statements
are an allowed shorthand method of writing
processes.
„Processes have a declaration and statement
section. Thestatement section contains only
sequential statements.
Sequential signal assignments have special
considerations.

variables, constants, data types, and subprograms may be
declared in processes.
„„Processes must contain either a wait statement or sensitivity list
(or would never quit running)
„
„All processes begin execution during simulator initialization.
Variables are initialized once and thereafter retain their relative
values

Process with Signals
„Contains only sequential statements
„Can access signals defined in architecture and entity
„Must contain either an explicit sensitivity list, or a wait
statement(s)
„Can have variable assignment and signal assignment
statements.

Sensitivity List
„PROCESS (sig1, sig2,...sigN)
„Events (changes) on any signal in sensitivity list will cause
process execution to
resume, after BEGIN statement
„Process execution continues until END process statement is
reached
„For synthesis, all signals which are read, typically must be
included in the sensitivity
list

Variable assignment statement replaces the current value
of a variable with a new value which is Specified by an
expression.
target_variable := expression;
Target_variable is a variable previously declared.
Expression is a statement using variables, signals, and
literals.
IMPORTANT : The named variable and the result of the
expression must be same type Statement executes in
zero simulation time Assignments can be made to a
scalar or to an array Variables declared within a process
cannot pass values outside of a process.
Variable assignment statement

Signal Assignment Statement
Signals are assigned values using a signal assignment statement The simplest
form of a signal assignment statement is
signal-object <= expression [ after delay-value ];
A signal assignment statement can appear within a process or outside of a
process. If it occurs outside of a process, it is considered to be a concurrent
signal assignment statement. This' is discussed in the next chapter. When a signal
assignment statement appears within a process, it is considered to be a sequential
signal assignment statement and is executed in sequence with respect to the other
sequential statements that appear within that process.
When a signal assignment statement is executed, the value of the expression is
computed and this value is scheduled to be assigned to the signal after the
specified delay. It is important to note that the expression is evaluated at the time
the statement is executed (which is the current simulation time) and not after the
specified delay. If no after clause is specified, the delay is assumed to be a
default delta delay.
Some examples of signal assignment statements are
COUNTER <= COUNTER+ "0010"; - Assign after a delta delay.
PAR <= PAR xor DIN after 12 ns;
Z <= (AO and A1) or (BO and B1) or (CO and C1) after 6 ns;

VHDL – BEHAVIORAL
MODELING
The process then suspends and waits for another
event to occur
The process statement itself can execute concurrently
with other concurrent statements, but internally, it
executes sequentially
The variable gets initialized to –1, then incremented
to zero
Any time an event occurs on A, this process is
executed
process(A)
variable EVENTS_ON_A:INTEGER:=-1;
begin
EVENTS_ON_A:= EVENTS_ON_A+1;
end process

VHDL – BEHAVIORAL
MODELING
Another example

VHDL – BEHAVIORAL MODELING
Signals are assigned values using a signal assignment
statement, The simplest form of a signal assignment
statement is
Signal-object <=expression [after delay-value];
A signal assignment statement can appear within or
outside of a process
 If outside a process, it is concurrent with the process statement
Within the process, it is sequential assignment statement.
 When the signal appears within the process, it is considered to
be a concurrent signal assignment statement.
When executed, the expression on the right side of
the assignment is evaluated at that time, not after any
specified delay, then assigned to the signal after any
specified delay
Signal Assignment Statement

VHDL – BEHAVIORAL
MODELING
Wait Statement – a alternate way to suspend a
process
3 forms of the wait statement
Can be done in a single wait statement
Examples

VHDL – BEHAVIORAL
MODELING
Another example using the wait statement, this time
in a process without a sensitivity list
Must have a sensitivity list or a wait statement, but
NOT both

if statement – selects statements for execution
based upon a condition
If s1=‘0’ then
If s0=‘0’ then
MUX_out<=“0001
else
MUX_out<=“0010
end if;
else
If s0=‘0’ then
MUX_out<=“0100
else
MUX_out<=“1000
end if;

2-input NOR gate done with if statements

case statement – selects one branch of execution from
a list of many based upon expression

HALF ADDER:
Program:
library IEEE;
entity halfadder_bm is
Port ( IP : in STD_LOGIC_VECTOR (1 downto
0); sum : out STD_LOGIC;
carry : out STD_LOGIC);
end halfadder_bm;

architecture Behavior of halfadder_bm is
begin
ha:Process(IP)
begin
if(IP="00")then
sum<='0';carry<='0';
else if(IP="01" or IP="10")then
else sum<='1';carry<='1';
end if;
end if;
end Process ha;
end Behavior;

architecture Behavioral of fulladder_bm is
begin
fa:process(a,b,c)
begin
if(a='0' and b='0' and c='0')then
else if(a='0' and b='0' and c='1')then

else sum<='1';carry<='1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process fa;
end Behavioral;

Comparator:
library IEEE;
entity comparator_bm is
Port ( x : in STD_LOGIC_VECTOR (7 downto
0);
y : in STD_LOGIC_VECTOR (7 downto 0);
eq,gt,lt : out STD_LOGIC);
end comparator_bm;

architecture Behavioral of comparator_bm is
begin
comp:process(x,y)
begin
if(x=y)then
eq<='1';lt<='0';gt<='0';
else if(x<y)then
eq<='0';lt<='1';gt<='0';
else
eq<='0';lt<='0';gt<='1';
end if;
end if;
end process comp;
end Behavioral;

The format of case statement is
case expression is
when choices => sequential statements
when choices =>sequential statements
-- can have any number of branches
when others=> sequential statements
end case

4 X 1 Mux:
Program:
library IEEE;
entity fx1mux is
Port ( ip : in STD_LOGIC_VECTOR (3 downto
0);
s : in STD_LOGIC_VECTOR (1 downto 0);
z : out STD_LOGIC);
end fx1mux;

architecture Behavioral of fx1mux is
begin
process(s,ip)
begin
case s is
when "00"=>z<=ip(0);
when "01"=>z<=ip(1);
when "10"=>z<=ip(2);
when others =>z<=ip(3);
end case;
end process;
end Behavioral;

1 X 8 demux:
Program:
library IEEE;
entity ox8 is
Port ( data : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
z : out STD_LOGIC_VECTOR (7 downto
0));
end ox8;

architecture Behavioral of ox8 is
begin
process(data,s)
begin
z<="00000000";
case s is
when "000"=>z(0)<=data;
when "001"=>z(1)<=data;
when "010"=>z(2)<=data;
when "011"=>z(3)<=data;
when "100"=>z(4)<=data;
when "101"=>z(5)<=data;
when "110"=>z(6)<=data;
when others =>z(7)<=data;
end case;
end process; end Behavioral;

Decoder:
Program:
library IEEE;
entity decoder_bm is
Port ( ip : in STD_LOGIC_VECTOR (2 downto 0);
op : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_bm;
architecture Behavioral of decoder_bm is
begin
decoder:process(ip)
begin
case(ip) is
when "000"=>op<="00000001";
when "001"=>op<="00000010";
when "010"=>op<="00000100";
when "011"=>op<="00001000";
when "100"=>op<="00010000";
when "101"=>op<="00100000";
when "110"=>op<="01000000";
when "111"=>op<="10000000";
when others=>null;
end case;
end process decoder;
end Behavioral;

Encoder:
Program:
library IEEE;
entity encoder_bm is
Port ( ip : in STD_LOGIC_VECTOR (7
downto 0);
op : out STD_LOGIC_VECTOR (2
downto 0));
end encoder_bm;

architecture Behavioral of encoder_bm is
begin
encoder: process(ip)
begin
if(ip="00000001")then
op<="000";
else if(ip="00000010")then
op<="001";

op<="010";
op<="011";
op<="100";
op<="101";
op<="110";
else op<="111";
end if;end if;end if;end if;end
if;
end if;
end if;
end process encoder;
end Behavioral;

VHDL – BEHAVIORAL
MODELING
Null statement – it does nothing, sometimes may need
to specify that nothing is to be done
null;

loop statement – used to iterate through a set of
sequential statements
Several types of loops used in examples below. The
syntax of loop statement is
Three types of iterations. The first is for iteration scheme
While iteration scheme
while Boolean expression
Third one is one no iteration scheme is s

VHDL – BEHAVIORAL
MODELING
exit statement – used to jump out of a loop, cannot
be used except inside a loop

next statement – can only be used inside a loop and
begins execution back at the beginning of the loop

VHDL – BEHAVIORAL
MODELING
assertion statement – used for modeling constraints
of an entity

VHDL – BEHAVIORAL
MODELING
report statement – can be used to generate a message
Example:
 report “This circuit does not work”

VHDL_Lecture_new1 [Autosaved].ppt

VHDL_Lecture_new1 [Autosaved].ppt

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