All about random stability in sv and UVM based testbench including examples. Represent through example and dig. Also explain how any process get seed for randomize.

1. Random Stability
-By Kashyap Adodariya

2. 2
Introduction
• Importance of random verification or constraint random
verification.
• Important parameter to take care during create a testbench.
̶ Recreation
̶ Stable Testbench
• Random stimulus relies on Random number generator (RNG).
̶ E.g. Xn+1 = (a Xn + c) mod m
Random Stability

3. 3
Common Practice for Seeding.
Random Stability
DO DON’T
Used Random
sources
Independent random
sources from seed.
No limited to small
subsets values
Source relies on
Physical randomness
Zero seed input.
Limited range of
seed values
Time and date
format
Bash Variable
$RANDOM

4. 4
What is Random Stability?
• Sequence of Random Number should be same for given
seed.
• Significance:
1. Consistent Results.
2. Replicating Bugs.
3. Testing Bug fixes.
Random Stability

5. 5
Affecting Factors for Random Stability
• Thread Locality.
• Hierarchical seeding.
Random Stability

6. 6
Reason for instability
1) A change in the order of random calls with a process.
2) Insertion of new processes before previously defined ones.
3) A change in the order of creation of forked processes.
4) A change in the order of object creation.
• $random and $dist_uniform($dist_*) are non-hierarchically seed.
Random Stability

7. 7
A change in the order of random calls with a process.
module test;
class pkt;
rand bit [7:0] data;
endclass: pkt
initial begin
pkt p;
int unsigned var1;
for (int i=0; i<5; i++) begin
var1 = $urandom();
$display("urandom before calling object new var1: %0h", var1);
end
p = new(); // Object new after for-loop
end
endmodule
module test1;
class pkt;
rand bit [7:0] data;
endclass: pkt
initial begin
pkt p;
int unsigned var1;
p = new(); // Object new before for-loop
for (int i=0; i<5; i++) begin
var1 = $urandom();
$display("urandom after calling object new var1: %0h", var1);
end
end
endmodule
Random Stability
Seed = S3 to S7
Seed = S8
Seed = S3
Seed = S4 to S8
Seed = S1
Seed = S2
Seed = S1
Seed = S2

8. 8
Insertion of new processes before previously defined ones
class pkt;
rand bit [7:0] data;
endclass: pkt
module test2;
initial begin
pkt p = new();
int unsigned var1,var2;
p.randomize();
$display("p->data %0h ", p.data);
fork begin
for (int i=0; i<3; i++) begin
var1 = $urandom();
$display("thread-block var1: %0h", var1);
end
end join
for (int i=0; i<3; i++) begin
var2 = $urandom();
$display("module-block var2: %0h", var2);
end
end
endmodule: test2
module test3;
initial begin
pkt p = new();
int unsigned var1,var2;
byte var3;
#1; $display("----------TEST3---------");
p.randomize();
$display("p->data %0h ", p.data);
for (int i=0; i<3; i++) begin
var3 = $urandom();
$display("thread-block var1: %0h", var1);
end
fork
begin
for (int i=0; i<3; i++) begin
var1= $urandom();
$display("thread-block var3: %0h", var3);
end
end
join
for (int i=0; i<3; i++) begin
var2 = $urandom();
$display("module-block var2: %0h", var2);
end
end
endmodule: test3
Random Stability
test2.Seed: S1
test2.initial.Seed:S2
test2.inital.p.Seed:S3
test2.initial.fork.var1.Seed: S5
test2.initial.var2.Seed: S4
test3.Seed:S1
test3.inital.p.Seed:S3
test3.initial.var3.Seed:S4
test3.initial.fork.var1.Seed:S6
test3.initial.var2.Seed: S5
Output
class pkt;
rand bit [7:0] data;
endclass: pkt
module test2;
initial begin
pkt p = new();
int unsigned var1,var2;
p.randomize();
$display("p->data %0h ", p.data);
fork begin
for (int i=0; i<3; i++) begin
var1 = $urandom();
$display("thread-block var1: %0h", var1);
end
end join
for (int i=0; i<3; i++) begin
var2 = $urandom();
$display("module-block var2: %0h", var2);
end
end
endmodule: test2
module test3;
initial begin
pkt p = new();
int unsigned var1,var2;
byte var3;
#1; $display("----------TEST3---------");
p.randomize();
$display("p->data %0h ", p.data);
for (int i=0; i<3; i++) begin
var3 = $urandom();
$display("thread-block var3: %0h", var3);
end
fork
begin
for (int i=0; i<3; i++) begin
var1= $urandom();
$display("thread-block var1: %0h", var1);
end
end
join
for (int i=0; i<3; i++) begin
var2 = $urandom();
$display("module-block var2: %0h", var2);
end
end
endmodule: test3

9. 9
A change in the order of object creation.
Random Stability
class test1;
//….
endclass: test1
module ex1;
test1 t1,t2,t3,t4;
initial begin
#1; $display("module ex1");
begin: b1
t1 = new("t1");
t1.randomize();
$display("t1.a = %0d",t1.a);
end: b1
begin: b2
t2 = new("t2");
t2.randomize();
$display("t2.a = %0d",t2.a);
end: b2
begin: b3
t3 = new("t3");
t3.randomize();
$display("t3.a = %0d",t3.a);
end: b3
begin: b4
t4 = new("t4");
t4.randomize();
$display("t4.a = %0d",t4.a);
end: b4
end
endmodule: ex1
module ex2;
test1 t1,t2,t3,t4;
initial begin
#1; $display("module ex2");
begin: b1
t2 = new("t2");
t2.randomize();
$display("t2.a = %0d",t2.a);
end: b1
begin: b2
t3 = new("t3");
t3.randomize();
$display("t3.a = %0d",t3.a);
end: b2
begin: b4
t4 = new("t4");
t4.randomize();
$display("t4.a = %0d",t4.a);
end: b4
begin: b3
t1 = new("t1");
t1.randomize();
$display("t1.a = %0d",t1.a);
end: b3
end
endmodule: ex2
initial.t1.Seed: S3
initial.t2.Seed: S4
initial.t3.Seed: S5
Top1.Seed: S1
Initial.Seed: S2
initial.t4.Seed: S6
initial.t2.Seed: S3
initial.t3.Seed: S4
initial.t4.Seed: S5
Top1.Seed: S1
Initial.Seed: S2
initial.t5.Seed: S6

10. 10
A change in the order of creation of forked processes.
class pkt;
rand bit [7:0] data;
endclass: pkt
module test1;
initial begin
pkt p = new();
int unsigned var1,var2,var3;
p.randomize();
$display("initial block p->data %0h ", p.data);
fork begin
for (int i=0; i<3; i++) begin
var1 = $urandom();
$display("thread-block var1: %0h", var1);
end
end
begin
for (int i=0; i<3; i++) begin
var2 = $urandom();
$display("thread-block var2: %0h", var2);
end
end
join
var3 = $urandom();
$display("initial block var3: %0h",var3);
end
endmodule: test1
module test2;
initial begin
pkt p = new();
int unsigned var1,var2,var3;
#1 $display("tTest2t");
p.randomize();
#1;$display("initial block p->data %0h ", p.data);
fork begin: th1
for (int i=0; i<3; i++) begin
var2 = $urandom();
$display("thread-block var2: %0h", var2);
end
end: th1
begin: th2
for (int i=0; i<3; i++) begin
var1 = $urandom();
$display("thread-block var1: %0h", var1);
end
end : th2
join
var3 = $urandom();
$display("initial block var3: %0h",var3);
end
endmodule: test2
Random Stability
test1.inital.p.Seed: S1
test1.inital.fork1.var1.Seed: S3
Top.initial.fork1.var3.Seed: S4
Top.initial.var3.Seed:S2
Top.initial.var3.Seed:S2
test1.inital.p.Seed: S1
test1.inital.fork1.var2.Seed: S4
Top.initial.fork1.var1.Seed: S3

11. 11
Achieve Hierarchical seeding stability
1) Controlling the creation of hierarchical elements.
2) Using a template stimulus generator.
3) Manually seeding.
11
Random Stability
module ex;
test1 t1,t2,t3;
initial begin
fork
begin
t1 = new("t1");
t1.srandom(12);
t1.randomize();
$display("t1.a = %0d",t1.a);
end
begin
t2 = new("t2");
t2.srandom(5);
t2.randomize();
$display("t2.a = %0d",t2.a);
end
join
end
endmodule: ex
ex.initial.fork.t1.seed: S(12)
ex.initial.fork.t2.seed: S(5)

12. 12
Understanding UVM Random Stability
• Random Areas in UVM testbench
̶ UVM_COMPONENTS
̶ Sequences, Sequence_item, transaction.
• By default UVM used Hashing algorithm.
• Debug using flag use_uvm_seeding.
Random Stability

13. 13
Basic Working of Hash Algorithm.
//psudo code only
class abc extends uvm_component;
`uvm_component_utils(abc)
function new(string name = "abc", uvm_component parent = null);
super.new(name,parent);
endfunction //new()
function void build_phase(uvm_phase phase);
xyz = XYZ::type_id::create("xyz",this);
...
pqr = PQR::type_id::create("pqr",this);
...
endfunction: build_phase
endclass //abc extends uvm_component
Random Stability

14. 14
UVM Component random stability
• Requirement
• Solutions
̶ Manual seeding.
̶ Relying on absolute execution path.
̶ Protected by own srandom() call.
• Limitations
̶ Thread stability.
̶ Calling randomize() method.
Figure: Adding the red component with
instantiations, forks and randomization (not shown),
should not change any random results in the blue
components
Random Stability

15. 15
UVM Component random stability example
Thread stability
class my_bfm extends uvm_component;
//…
task run_phase(uvm_phase phase);
int unsigned response_delay;
//…
response_delay = $urandom_range(0, 20);
randomize(response_delay) with
{(response_delay >= 0) && (response_delay <= 20);};
//…
endtask
Endclasss
• Random Systemtask used SV based hierarchy
seeding.
• In run_phase() try to used randomize() method.
• Avoid to use random system tasks as much as
possible.
Random Stability

16. 16
UVM Component random stability example (Cont…)
Calling randomize() method
class comp1 extends uvm_component;
`uvm_component_utils(comp1)
rand int a;
//…
endclass
class env extends uvm_component;
`uvm_component_utils(env)
rand int c; rand int d;
rand comp1 rand_comp1;
function void build_phase (uvm_phase phase);
assert(randomize(c));
`uvm_info("env",$sformatf("c = %0ht d = %0h",c,d),UVM_LOW)
rand_comp1 = comp1::type_id::create("rand_copm1",this);
assert(randomize(rand_comp1)); //1
assert(rand_comp1.randomize()); //2
`uvm_info("env",$sformatf("rand_comp1.a = %0h",
rand_comp1.a),UVM_LOW)
assert(randomize(d));
`uvm_info("env",$sformatf("c = %0ht d = %0h",c,d),UVM_LOW)
endfunction
endclass
Random Stability
Before randomize comp1
Option 1 Result
Option 2 Result
https://edaplayground.com/x/avTE

17. 17
UVM sequence and sequence_item
• Requirement
• Solution
̶ Isolated sequence and sequence_item.
• Limitations
̶ Unique naming Enforced.
̶ Reseeding timing doesn’t match.
• Used `uvm_do macro
Random Stability

18. 18
UVM sequence and sequence_item example
class my_sub_sequence extends uvm_sequence #(my_item);
rand int unsigned num_of_items;
//…
endclass
class my_sequence extends uvm_sequence#(my_item);
my_sub_sequence sub_sequence;
task body();
// using create/randomize/start
sub_sequence = my_sub_sequence::type_id::create(“sub_sequence”);
sub_sequence.randomize();
sub_sequence.start(get_sequencer(),this);
//using `uvm_do
`uvm_do(sub_sequence)
endtask
endclass
class my_sequence extends
uvm_sequence#(my_item);
my_sub_sequence sub_sequence;
task body();
// using create/randomize/start
sub_sequence =
my_sub_sequence::type_id::create(“sub_sequence”);
sub_sequence.set_item_context(this, get_sequencer());
sub_sequence.randomize();
sub_sequence.start(get_sequencer(),this);
endtask
endclass
https://www.edaplayground.com/x/vhhp
Random Stability

19. 19
Conclusion
• Achieve Random Stability.
̶ Control the order process creation.
̶ Isolated seeds using template stimulus generator
̶ Manually seed to each element.
• Random system task used carefully.
• In nutshell Random Stability achieve by locking seeds
for each elements.
Random Stability

20. 20
Reference
[1]. "IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification
Language," IEEE Std 1800-2009, 2009.
[2]. Smith, D., 2013. Random Stability in SystemVerilog. In: D. Smith, ed., 1st ed. [online] Austin,
Texas, USA: Doulos. Available at: https://www.doulos.com/media/1293/snug2013_sv_random_
stability_paper.pdf [Accessed 15 February 2022].
[3]. UVM 1.1a Reference, www.uvmworld.org
[4]. A. Efody, "UVM Random Stability Don’t leave it to chance", S3.amazonaws.com, 2012. [Online].
Available: https://s3.amazonaws.com/verificationacademy-news/DVCon2012/Papers/MGC_DV
Con_12_UVM_Random_Stability_Don't_Leave_it_to_Chance.pdf. [Accessed: 17- Feb- 2022].
20
Random Stability

21. 21
Thank You
Random Stability