This document discusses the design of look-up tables as databases implemented on field programmable gate arrays (FPGAs). It describes implementing both simple and large random access memory (RAM) models using look-up tables and VHDL. Experimental methods including specification, verification, and implementation are used. The RAM designs are simulated and tested on a Spartan-3E FPGA. Results show the RAM design has a time delay of around 6.546ns and uses few logic resources on the FPGA.

1. Dr. Ferry Wahyu Wibowo, S.Si., M.Cs.
D E P A R T M E N T O F I N F O R M A T I C S
U N I V E R S I T A S A M I K O M Y O G Y A K A R T A
f e r r y . w @ a m i k o m . a c . i d
DESIGN OF LOOK-UP TABLE AS
DATABASE BASED-ON FIELD
PROGRAMMABLE GATE ARRAY
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2. INTRODUCTION
 Field Programmable Gate Arrays (FPGAs) have been
used in wide range of applications of industrial,
instrumentation, distributed arithmatics , digital
signal processing, telecommunication, etc .
 FPGA architecture has an effect on the quality of
device’s speed performance, area efficiency, and
power consumption.
 The implementation of RAM using VHDL.
Simple RAM model based on Look-Up Table (LUT).
Large RAM model based on Look-Up Table (LUT).
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3. Random Access Memory
 The random access memory (RAM) is a type of
semiconductor memory that is built to hold
permanent data.
 In the RAM operation, new data can be written and
data can be read from it.
 For some RAMs the data are stored when during the
manufacturing process, and for other RAMs the data
can be entered electrically. This process is called
programming or burning in the RAM. RAMs can
be reprogrammed.
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4. Random Access Memory (Cont’d)
 The structure of a RAM IC is very complex.
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5. RESEARCH METHOD
Experimental has been done in this research using
methods :
Specification
Verification
Implementation
Tools have been used in this research are
 FPGA Spartan-3E starter kit,
 Very High Speed Integrated Circuit Hardware
Description Language (VHDL) that is written in
Xilinx software ISE9.2i.
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6. RESULT AND DISCUSSION (Cont’d)
 All of the designs have been verified and simulated in
ISE9.2i Xilinx, and they have same waveform shown
as figure 1.
Figure 1. Waveform Diagram of RAM
Time delay of RAM design is about 6.546ns, obtained
from 5.194ns logic and 1.352 ns route.
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7. RESULT AND DISCUSSION (Cont’d)
Floorplan of RAM design on
FPGAs
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8. RESULT AND DISCUSSION (Cont’d)
Table 1. Components used on FPGA Spartan-3E
Component Used
Components
Available
on FPGAs
Slices 4 (0%) 4656
4 input LUTs 8 (0%) 9312
IO 11 -
Bonded IOB 11 (4%) 232
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9. References
https://ferrywahyuwibowo.my.id
https://ferrywahyuwibowo.my.id/index.php/396/xilinx-ise-simulator/
https://ferrywahyuwibowo.my.id/index.php/393/tutorial-of-xilinx-webpack-and-
modelsim-xe/
https://ferrywahyuwibowo.my.id/index.php/192/2-1-multiplexer-using-vhdl/
https://ferrywahyuwibowo.my.id/index.php/186/vhdl-fpga/
https://ferrywahyuwibowo.my.id/index.php/180/notes-for-fpga-designer/
https://ferrywahyuwibowo.my.id/index.php/175/fpga-dan-asic/
https://ferrywahyuwibowo.my.id/index.php/172/memulai-belajar-fpga/
https://ferrywahyuwibowo.my.id/index.php/168/memulai-proyek-sederhana-
menggunakan-fpga/
https://ferrywahyuwibowo.my.id/index.php/165/vhdl-menggunakan-xilinx-ise/
https://ferrywahyuwibowo.my.id/index.php/396/xilinx-ise-simulator/

10. END OF PRESENTATION
THANK YOU
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