SlideShare a Scribd company logo

Programmable Switches for Programmable Logic Devices

•
•
Usha Mehta
Usha Mehta

Programmable Switches, FPGA, EEPROM, EPROM, Fuse, Antifuse

Engineering
1 of 26
Programmable Switches Dr Usha Mehta usha.mehta@nirmauni.ac.in
Acknowledgement This presentation has been summarized from various books, papers, websites and presentations related to the topic all over the world. I couldn’t remember where these large pull of hints and work come from. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Usha Mehta 08-12-2023
Programmable Switches Programmable switches are used in PLD for • Connections • Wire • Logic • Input-Output • Configurations • Logic Blocks 3 Usha Mehta 08-12-2023
Ideal Programmable Switch • An FPLD contains thousands of such programmable switches. • Hence the switches should • Occupy very less area • Have very low ON resistance and very high OFF resistance • Have very less parasitic capacitance • Easily fabricated in large number with high reliability 4 Usha Mehta 08-12-2023
• Programmable switches may be • Permanent • One time Programmable • Non Permanent • Reprogrammable 5 Usha Mehta 08-12-2023
Fuse • One Time Programmable (OTP) • Initially: SHORT, • After programming: OPEN 6 Usha Mehta 08-12-2023
Array Logic by Fuse 7 Usha Mehta 08-12-2023
Fuse Programming 8 Usha Mehta 08-12-2023
Fuse Programmed Logic Array 9 Usha Mehta 08-12-2023
Antifuse Technology • Opposite to Fuse • Initially: OPEN • Programmed by forcing a current through it: SHORT • Actel calls it “Programmable Low-Impedance Circuit Element (PLICE)” 10 Usha Mehta 08-12-2023
Antifuse Structure • Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive. 11 Usha Mehta 08-12-2023
MOS Structure of Antifuse 12 Usha Mehta 08-12-2023
ACTEL’s PLICE Structure 13 Usha Mehta 08-12-2023
Antifuse: Advantages-Disadvantages • Advantages • Very small in size hence allows denser switch population • Low series resistance • Low parasitic capacitance • Disadvantages • One time programmable • Requires extra circuitry to deliver the high programming voltage • Requires a specific process ( not same as normal standard integrated circuit process) 14 Usha Mehta 08-12-2023
Static RAM Programmable Switch • Use SRAM Cell to control pass transistor or multiplexer by the bit-content in the SRAM cell. 15 Usha Mehta 08-12-2023
SRAM Cell 16 Usha Mehta 08-12-2023
• Disadvantages • Volatile • External Permanent memory required • Large Area Required • Advantages • Easily and quickly reprogrammable • Requires only standard integrated circuit process technology for fabrication. No special requirements like Antifuse 17 Usha Mehta 08-12-2023
EPROM Technology • Use of Erasable Programmable Transistor as switch • It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. 18 Usha Mehta 08-12-2023
EPROM Structure • A FET with floating gate • The floating gate has no connections to other parts of the integrated circuit and is completely insulated by the surrounding layers of oxide • Storing data requires applying a higher voltage to the transistors. • This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode. • When the high voltage is removed, the electrons are trapped on the electrode. • Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades. 19 Usha Mehta 08-12-2023
EPROM as switch • Become Open path when programmed because of the electrons trapped on floating gate raise the threshold voltage of n Channel EPROM above VDD • Erasable/Reprogra mmable by applying UV light 20 Usha Mehta 08-12-2023
NOR based Flash Memory 21 Usha Mehta 08-12-2023
Comparison of Switching Technologies SRAM Antifuse EPROM EEPROM Manufacturi ng Process Easy Hard Hard Hard Reprogramm able? Yes (in circuit) No Yes (Out of Circuit) Yes (in circuit) Size Large (12X) Small (1X) Small Small ON Resistance 600-800 Ohm 100-500 Ohm 1-4K 1-4K OFF capacitance (fF) 10-50 1-3 10-50 10-50 Power Consumptio n Very less less High High Volatile? Yes No No No 22 Usha Mehta 08-12-2023
Switching in FPGA 23 Usha Mehta 08-12-2023
Market Use of Programmable Switches • Actel: Antifuse • Xilinx: SRAM • Altera: EEPROM/FLASH 24 Usha Mehta 08-12-2023
Radiation Immunity of Programmable Switches Antifuse SRAM FLASH Configuration has been designated as hard regarding SEEs. Configuration has been designated as the most susceptible portion of circuitry. Configuration has been designated as hard (but NOT immune) regarding SEEs No need of mitigation Strong need of mitigation No need of mitigation 08-12-2023 Usha Mehta 25
Thank you! 26 Usha Mehta 08-12-2023

Recommended

Programmable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDProgrammable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDUsha Mehta
 
Field Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureField Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureUsha Mehta
 
8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdf8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdfUsha Mehta
 
9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdf9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdfUsha Mehta
 
2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdf2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdfUsha Mehta
 
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdfUsha Mehta
 
7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdfUsha Mehta
 
13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdfUsha Mehta
 

Recommended

Programmable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDProgrammable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDUsha Mehta
 
Field Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureField Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureUsha Mehta
 
8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdf8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdfUsha Mehta
 
9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdf9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdfUsha Mehta
 
2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdf2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdfUsha Mehta
 
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdfUsha Mehta
 
7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdfUsha Mehta
 
13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdfUsha Mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designUsha Mehta
 
6 verification tools
6 verification tools6 verification tools
6 verification toolsUsha Mehta
 
Digital VLSI Design : Combinational Circuit
Digital VLSI Design : Combinational CircuitDigital VLSI Design : Combinational Circuit
Digital VLSI Design : Combinational CircuitUsha Mehta
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_designUsha Mehta
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehtaUsha Mehta
 
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlocksPhysical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlockseInfochips (An Arrow Company)
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysisUsha Mehta
 
Powerplanning
PowerplanningPowerplanning
PowerplanningVLSI SYSTEM Design
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testingUsha Mehta
 
ASIC Design Flow | Physical Design | VLSI
ASIC Design Flow | Physical Design | VLSI ASIC Design Flow | Physical Design | VLSI
ASIC Design Flow | Physical Design | VLSI Jayant Suthar
 
5 verification methods
5 verification methods5 verification methods
5 verification methodsUsha Mehta
 
Timing closure document
Timing closure documentTiming closure document
Timing closure documentAlan Tran
 
Floor plan & Power Plan
Floor plan & Power Plan Floor plan & Power Plan
Floor plan & Power Plan Prathyusha Madapalli
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfUsha Mehta
 
1 introduction to vlsi physical design
1 introduction to vlsi physical design1 introduction to vlsi physical design
1 introduction to vlsi physical designsasikun
 
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planningUsha Mehta
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedyUsha Mehta
 
vlsi design flow
vlsi design flowvlsi design flow
vlsi design flowAnish Gupta
 
Pd flow i
Pd flow iPd flow i
Pd flow iAlok Kumar
 
Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001BeimarHerediaSaigua1
 
5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDURaritan
 

More Related Content

What's hot

Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designUsha Mehta
 
6 verification tools
6 verification tools6 verification tools
6 verification toolsUsha Mehta
 
Digital VLSI Design : Combinational Circuit
Digital VLSI Design : Combinational CircuitDigital VLSI Design : Combinational Circuit
Digital VLSI Design : Combinational CircuitUsha Mehta
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_designUsha Mehta
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehtaUsha Mehta
 
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlocksPhysical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlockseInfochips (An Arrow Company)
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysisUsha Mehta
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testingUsha Mehta
 
ASIC Design Flow | Physical Design | VLSI
ASIC Design Flow | Physical Design | VLSI ASIC Design Flow | Physical Design | VLSI
ASIC Design Flow | Physical Design | VLSI Jayant Suthar
 
5 verification methods
5 verification methods5 verification methods
5 verification methodsUsha Mehta
 
Timing closure document
Timing closure documentTiming closure document
Timing closure documentAlan Tran
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfUsha Mehta
 
1 introduction to vlsi physical design
1 introduction to vlsi physical design1 introduction to vlsi physical design
1 introduction to vlsi physical designsasikun
 
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planningUsha Mehta
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedyUsha Mehta
 
vlsi design flow
vlsi design flowvlsi design flow
vlsi design flowAnish Gupta
 

What's hot (20)

Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi design
 
6 verification tools
6 verification tools6 verification tools
6 verification tools
 
Digital VLSI Design : Combinational Circuit
Digital VLSI Design : Combinational CircuitDigital VLSI Design : Combinational Circuit
Digital VLSI Design : Combinational Circuit
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehta
 
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate BlocksPhysical Design Flow Challenges at 28nm on Multi-million Gate Blocks
Physical Design Flow Challenges at 28nm on Multi-million Gate Blocks
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis
 
Powerplanning
PowerplanningPowerplanning
Powerplanning
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testing
 
ASIC Design Flow | Physical Design | VLSI
ASIC Design Flow | Physical Design | VLSI ASIC Design Flow | Physical Design | VLSI
ASIC Design Flow | Physical Design | VLSI
 
5 verification methods
5 verification methods5 verification methods
5 verification methods
 
Timing closure document
Timing closure documentTiming closure document
Timing closure document
 
Floor plan & Power Plan
Floor plan & Power Plan Floor plan & Power Plan
Floor plan & Power Plan
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdf
 
1 introduction to vlsi physical design
1 introduction to vlsi physical design1 introduction to vlsi physical design
1 introduction to vlsi physical design
 
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planning
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
 
vlsi design flow
vlsi design flowvlsi design flow
vlsi design flow
 
Pd flow i
Pd flow iPd flow i
Pd flow i
 

Similar to Programmable Switches for Programmable Logic Devices

5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDURaritan
 
bluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinhabluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinhaShubham Sinha
 
ELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKERELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKERganeshbehera6
 
Circuit bending presentation
Circuit bending presentationCircuit bending presentation
Circuit bending presentationDan Wilson
 
Presentation smart city presentation by cs electric (4)
Presentation smart city presentation by cs electric (4)Presentation smart city presentation by cs electric (4)
Presentation smart city presentation by cs electric (4)Mahesh Chandra Manav
 
Installation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plantsInstallation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plantsGomathy Sengottaiyan
 
energy-harvesting-pres-final-std
energy-harvesting-pres-final-stdenergy-harvesting-pres-final-std
energy-harvesting-pres-final-stdDaniele Costarella
 
Campus networks best practices core and edges network
Campus networks best practices core and edges networkCampus networks best practices core and edges network
Campus networks best practices core and edges networkAshish Thomas
 
KL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdfKL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdfSysteDesig
 
Individual project
Individual projectIndividual project
Individual projectMinu Pradeep
 
Clap switch
Clap switch Clap switch
Clap switch OmWakade
 
THE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptxTHE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptxArdiansyah58870
 
Printed circuit board
Printed circuit boardPrinted circuit board
Printed circuit boardSuhail Ahmed
 

Similar to Programmable Switches for Programmable Logic Devices (20)

Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001Ca vd4 50k-a(en)y_1vcp000001
Ca vd4 50k-a(en)y_1vcp000001
 
5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU5 Reasons You Need the Latest Generation of iPDU
5 Reasons You Need the Latest Generation of iPDU
 
Residential wiring PPT.pptx
Residential wiring PPT.pptxResidential wiring PPT.pptx
Residential wiring PPT.pptx
 
bluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinhabluetooth controlled home automation using arduino by shubham sinha
bluetooth controlled home automation using arduino by shubham sinha
 
ELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKERELECTRONIC CIRCUIT BREAKER
ELECTRONIC CIRCUIT BREAKER
 
Circuit bending presentation
Circuit bending presentationCircuit bending presentation
Circuit bending presentation
 
Presentation smart city presentation by cs electric (4)
Presentation smart city presentation by cs electric (4)Presentation smart city presentation by cs electric (4)
Presentation smart city presentation by cs electric (4)
 
Installation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plantsInstallation and troubleshooting of solar pv power plants
Installation and troubleshooting of solar pv power plants
 
energy-harvesting-pres-final-std
energy-harvesting-pres-final-stdenergy-harvesting-pres-final-std
energy-harvesting-pres-final-std
 
Campus networks best practices core and edges network
Campus networks best practices core and edges networkCampus networks best practices core and edges network
Campus networks best practices core and edges network
 
KL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdfKL1034 Lect2 Electrical wiring.pdf
KL1034 Lect2 Electrical wiring.pdf
 
Wiring a ring main
Wiring a ring mainWiring a ring main
Wiring a ring main
 
Fuses_Lec_1.pptx
Fuses_Lec_1.pptxFuses_Lec_1.pptx
Fuses_Lec_1.pptx
 
Individual project
Individual projectIndividual project
Individual project
 
Clap switch
Clap switch Clap switch
Clap switch
 
VLSI Power Reduction
VLSI Power ReductionVLSI Power Reduction
VLSI Power Reduction
 
THE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptxTHE MIDDLE TEST OF ENGLISH II.pptx
THE MIDDLE TEST OF ENGLISH II.pptx
 
Single core and multi core cables
Single core and multi core cablesSingle core and multi core cables
Single core and multi core cables
 
SoC Power Reduction
SoC Power ReductionSoC Power Reduction
SoC Power Reduction
 
Printed circuit board
Printed circuit boardPrinted circuit board
Printed circuit board
 

More from Usha Mehta

Basic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysBasic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysUsha Mehta
 
5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdfUsha Mehta
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossingUsha Mehta
 
9 semiconductor memory
9 semiconductor memory9 semiconductor memory
9 semiconductor memoryUsha Mehta
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_designUsha Mehta
 
3 test economic_test_equipments_yield
3 test economic_test_equipments_yield3 test economic_test_equipments_yield
3 test economic_test_equipments_yieldUsha Mehta
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designUsha Mehta
 
BUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignBUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignUsha Mehta
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Usha Mehta
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
 

More from Usha Mehta (12)

Basic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysBasic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate Arrays
 
5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing
 
9 semiconductor memory
9 semiconductor memory9 semiconductor memory
9 semiconductor memory
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design
 
3 test economic_test_equipments_yield
3 test economic_test_equipments_yield3 test economic_test_equipments_yield
3 test economic_test_equipments_yield
 
1 why to_test
1 why to_test1 why to_test
1 why to_test
 
1 why to_test
1 why to_test1 why to_test
1 why to_test
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_design
 
BUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignBUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI Design
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)
 

Recently uploaded

(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Serviceranjana rawat
 
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...RajaP95
 
(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...ranjana rawat
 
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICSAPPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICSKurinjimalarL3
 
Software Development Life Cycle By Team Orange (Dept. of Pharmacy)
Software Development Life Cycle By Team Orange (Dept. of Pharmacy)Software Development Life Cycle By Team Orange (Dept. of Pharmacy)
Software Development Life Cycle By Team Orange (Dept. of Pharmacy)Suman Mia
 
HARMONY IN THE NATURE AND EXISTENCE - Unit-IV
HARMONY IN THE NATURE AND EXISTENCE - Unit-IVHARMONY IN THE NATURE AND EXISTENCE - Unit-IV
HARMONY IN THE NATURE AND EXISTENCE - Unit-IVRajaP95
 
KubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghlyKubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghlysanyuktamishra911
 
Coefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxCoefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxAsutosh Ranjan
 
Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...
Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...
Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...Christo Ananth
 
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...Dr.Costas Sachpazis
 
SPICE PARK APR2024 ( 6,793 SPICE Models )
SPICE PARK APR2024 ( 6,793 SPICE Models )SPICE PARK APR2024 ( 6,793 SPICE Models )
SPICE PARK APR2024 ( 6,793 SPICE Models )Tsuyoshi Horigome
 
Introduction and different types of Ethernet.pptx
Introduction and different types of Ethernet.pptxIntroduction and different types of Ethernet.pptx
Introduction and different types of Ethernet.pptxupamatechverse
 
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...Call Girls in Nagpur High Profile
 
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur EscortsCall Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur EscortsCall Girls in Nagpur High Profile
 
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete Record
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete RecordCCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete Record
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete RecordAsst.prof M.Gokilavani
 
UNIT-III FMM. DIMENSIONAL ANALYSIS
UNIT-III FMM. DIMENSIONAL ANALYSISUNIT-III FMM. DIMENSIONAL ANALYSIS
UNIT-III FMM. DIMENSIONAL ANALYSISrknatarajan
 
Extrusion Processes and Their Limitations
Extrusion Processes and Their LimitationsExtrusion Processes and Their Limitations
Extrusion Processes and Their Limitations120cr0395
 
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escortsranjana rawat
 

Recently uploaded (20)

★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
★ CALL US 9953330565 ( HOT Young Call Girls In Badarpur delhi NCR
 
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
(RIA) Call Girls Bhosari ( 7001035870 ) HI-Fi Pune Escorts Service
 
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
IMPLICATIONS OF THE ABOVE HOLISTIC UNDERSTANDING OF HARMONY ON PROFESSIONAL E...
 
(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANJALI) Dange Chowk Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
 
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICSAPPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
APPLICATIONS-AC/DC DRIVES-OPERATING CHARACTERISTICS
 
Software Development Life Cycle By Team Orange (Dept. of Pharmacy)
Software Development Life Cycle By Team Orange (Dept. of Pharmacy)Software Development Life Cycle By Team Orange (Dept. of Pharmacy)
Software Development Life Cycle By Team Orange (Dept. of Pharmacy)
 
HARMONY IN THE NATURE AND EXISTENCE - Unit-IV
HARMONY IN THE NATURE AND EXISTENCE - Unit-IVHARMONY IN THE NATURE AND EXISTENCE - Unit-IV
HARMONY IN THE NATURE AND EXISTENCE - Unit-IV
 
KubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghlyKubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghly
 
Coefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxCoefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptx
 
DJARUM4D - SLOT GACOR ONLINE | SLOT DEMO ONLINE
DJARUM4D - SLOT GACOR ONLINE | SLOT DEMO ONLINEDJARUM4D - SLOT GACOR ONLINE | SLOT DEMO ONLINE
DJARUM4D - SLOT GACOR ONLINE | SLOT DEMO ONLINE
 
Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...
Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...
Call for Papers - Educational Administration: Theory and Practice, E-ISSN: 21...
 
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
 
SPICE PARK APR2024 ( 6,793 SPICE Models )
SPICE PARK APR2024 ( 6,793 SPICE Models )SPICE PARK APR2024 ( 6,793 SPICE Models )
SPICE PARK APR2024 ( 6,793 SPICE Models )
 
Introduction and different types of Ethernet.pptx
Introduction and different types of Ethernet.pptxIntroduction and different types of Ethernet.pptx
Introduction and different types of Ethernet.pptx
 
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
Top Rated Pune Call Girls Budhwar Peth ⟟ 6297143586 ⟟ Call Me For Genuine Se...
 
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur EscortsCall Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
 
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete Record
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete RecordCCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete Record
CCS335 _ Neural Networks and Deep Learning Laboratory_Lab Complete Record
 
UNIT-III FMM. DIMENSIONAL ANALYSIS
UNIT-III FMM. DIMENSIONAL ANALYSISUNIT-III FMM. DIMENSIONAL ANALYSIS
UNIT-III FMM. DIMENSIONAL ANALYSIS
 
Extrusion Processes and Their Limitations
Extrusion Processes and Their LimitationsExtrusion Processes and Their Limitations
Extrusion Processes and Their Limitations
 
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
 

Programmable Switches for Programmable Logic Devices

  • 1. Programmable Switches Dr Usha Mehta usha.mehta@nirmauni.ac.in
  • 2. Acknowledgement This presentation has been summarized from various books, papers, websites and presentations related to the topic all over the world. I couldn’t remember where these large pull of hints and work come from. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Usha Mehta 08-12-2023
  • 3. Programmable Switches Programmable switches are used in PLD for • Connections • Wire • Logic • Input-Output • Configurations • Logic Blocks 3 Usha Mehta 08-12-2023
  • 4. Ideal Programmable Switch • An FPLD contains thousands of such programmable switches. • Hence the switches should • Occupy very less area • Have very low ON resistance and very high OFF resistance • Have very less parasitic capacitance • Easily fabricated in large number with high reliability 4 Usha Mehta 08-12-2023
  • 5. • Programmable switches may be • Permanent • One time Programmable • Non Permanent • Reprogrammable 5 Usha Mehta 08-12-2023
  • 6. Fuse • One Time Programmable (OTP) • Initially: SHORT, • After programming: OPEN 6 Usha Mehta 08-12-2023
  • 7. Array Logic by Fuse 7 Usha Mehta 08-12-2023
  • 9. Fuse Programmed Logic Array 9 Usha Mehta 08-12-2023
  • 10. Antifuse Technology • Opposite to Fuse • Initially: OPEN • Programmed by forcing a current through it: SHORT • Actel calls it “Programmable Low-Impedance Circuit Element (PLICE)” 10 Usha Mehta 08-12-2023
  • 11. Antifuse Structure • Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive. 11 Usha Mehta 08-12-2023
  • 12. MOS Structure of Antifuse 12 Usha Mehta 08-12-2023
  • 14. Antifuse: Advantages-Disadvantages • Advantages • Very small in size hence allows denser switch population • Low series resistance • Low parasitic capacitance • Disadvantages • One time programmable • Requires extra circuitry to deliver the high programming voltage • Requires a specific process ( not same as normal standard integrated circuit process) 14 Usha Mehta 08-12-2023
  • 15. Static RAM Programmable Switch • Use SRAM Cell to control pass transistor or multiplexer by the bit-content in the SRAM cell. 15 Usha Mehta 08-12-2023
  • 17. • Disadvantages • Volatile • External Permanent memory required • Large Area Required • Advantages • Easily and quickly reprogrammable • Requires only standard integrated circuit process technology for fabrication. No special requirements like Antifuse 17 Usha Mehta 08-12-2023
  • 18. EPROM Technology • Use of Erasable Programmable Transistor as switch • It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. 18 Usha Mehta 08-12-2023
  • 19. EPROM Structure • A FET with floating gate • The floating gate has no connections to other parts of the integrated circuit and is completely insulated by the surrounding layers of oxide • Storing data requires applying a higher voltage to the transistors. • This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode. • When the high voltage is removed, the electrons are trapped on the electrode. • Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades. 19 Usha Mehta 08-12-2023
  • 20. EPROM as switch • Become Open path when programmed because of the electrons trapped on floating gate raise the threshold voltage of n Channel EPROM above VDD • Erasable/Reprogra mmable by applying UV light 20 Usha Mehta 08-12-2023
  • 21. NOR based Flash Memory 21 Usha Mehta 08-12-2023
  • 22. Comparison of Switching Technologies SRAM Antifuse EPROM EEPROM Manufacturi ng Process Easy Hard Hard Hard Reprogramm able? Yes (in circuit) No Yes (Out of Circuit) Yes (in circuit) Size Large (12X) Small (1X) Small Small ON Resistance 600-800 Ohm 100-500 Ohm 1-4K 1-4K OFF capacitance (fF) 10-50 1-3 10-50 10-50 Power Consumptio n Very less less High High Volatile? Yes No No No 22 Usha Mehta 08-12-2023
  • 24. Market Use of Programmable Switches • Actel: Antifuse • Xilinx: SRAM • Altera: EEPROM/FLASH 24 Usha Mehta 08-12-2023
  • 25. Radiation Immunity of Programmable Switches Antifuse SRAM FLASH Configuration has been designated as hard regarding SEEs. Configuration has been designated as the most susceptible portion of circuitry. Configuration has been designated as hard (but NOT immune) regarding SEEs No need of mitigation Strong need of mitigation No need of mitigation 08-12-2023 Usha Mehta 25