2. 11/22/2023 VLSI Technology Trends... 2
Acknowledgement
This presentation has been summarized from various
books, papers, websites and presentations on VLSI
Design and its various topics all over the world. I
couldn’t remember where these large pull of hints and
work come from. However, I’d like to thank all
professors and scientists who created such a good work
on this emerging field. Without those efforts in this very
emerging technology, these notes and slides can’t be
finished.
NOTE: The figures, text etc included in slides are
borrowed from various books’ websites, authors’ books,
websites, pages and other sources for academic purpose
only. The instructor does not claim any originality.
13. 11/22/2023 VLSI Technology Trends... 13
The first Computer ENIAC using Valve
and Relays
• May 1944
• first ever general purpose electronic
computer
• by a team lead by J.P.Eckert and
J.W.Mauchly
• more than 18,000 valves, 100 by 10
by 3 feet, weight 30 tons.
• Faster than anything that had been
built previously; multiplication in
under 3 ms.
• Described as being “Faster than
thought”.
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Why Moore’s Law sustained…..?
(point of view:2)
Transistor
Scaling
Better
Performance
Market Growth
Investment
35. 11/22/2023 VLSI Technology Trends... 35
Reduction in Size
• Classical Scaling
• Reduction in L, W, TOX, VDD
• Second Age of Scaling (Equivalence Scaling)
• Reduction in L, W, TOX, VDD
• Channel Material
• Strained Silicon (SiGe)
• Stack Material
• High K
• Gate Material
• Metal Gate
• Structure
• Multi Gate
• FDSOI
• PDSOI
• Third Age of Scaling
38. 11/22/2023 VLSI Technology Trends... 38
• Constant Voltage
Scaling
• Vdd constant
• More preferable
because of
peripherals
• Power consumption
increases by …..
• Power density
increases by 3
• Constant Field Scaling
• Seems ideal but Not a
feasible option
• to keep new chips
compatible with existing
chips, voltages cannot be
scaled arbitrarily.
• Peripherals require
certain voltage levels at
inputs and outputs
• Multiple supply voltages
• Complicated Level shifter
arrangement
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Effects of Scaling
• Short Channel Effects
• Narrow channel Effects
• Subthreshold Conduction
• Punch through
• Hot electrons/hot carriers
• Electromigration
• ESD
• Electric Overstress…..
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• In view of number of road blocks in standard CMOS
scaling, new device architectures were adopted in
second generation of scaling.
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Strained MOSFET
• Because of constant voltage scaling, the electric field is
increased. Strong vertical fields resulting from large Vgs cause
the carriers to scatter against the surface and also reduce the
carrier mobility. This effect is called mobility degradation
• The links between the silicon atoms become stretched - thereby
leading to strained silicon. Moving these silicon atoms farther
apart reduces the atomic forces that interfere with the
movement of electrons through the transistors and thus
better mobility
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Limitation….
• Gate Oxide thickness can not be scaled down beyond a
limit because
• Processing difficulties in growing thin uniform oxide layer (
nonuniform oxide growth “pinholes” causes shorts between
gate and substrate)
• Oxide breakdown
• Thickness of SiO₂ layer required in 45nm technology is
about 1.2nm (4 atom layers deep!!)
• Gate oxide is running out of atoms
• Quantum nature of channel electron dominates.
• Tunnelling/leakage current IG
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High K Material
• If Gate Oxide thickness can not be reduced, can we
increase the quality of gate oxide to give higher
capacitance at same thickness?
• High K Material for gate oxide to increase the
insulator capacitance while keeping a thicker
oxide..
• to avoid tunnelling through the gate oxide
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Metal-Polysilicon-Metal
• Earlier : Metal Gate
• Earlier at 5V supply, metal gates were used
• Then: Polysilicon Gate
• At lower voltages and scaling, polysilicon gate used
because of fabrication process ease.
• After initial doping, very high temp. annealing was
required during which metal gates would melt
• Again: Metal Gate
• When SiO2 is replaced with High-K material, it was
found that PolySi and High K Material were not
compatible, So polySi was replaced by metal.
• After 45nm (Intel) and 28nm (TSMC), again back to
metal gates
• To avoid poly-depletion at the poly oxide interface.
• At smaller scales, the need for a higher Vt has become
important again due to problems of leakage.
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HKMG MOSFET
• Intel’s announcement, January 26, 2007
• Hafnium-based high-k material
• Effective Oxide Thickness = 1nm
• Specific gate metals ( Intel’s trade secret)
• Different Metals for NMOS and PMOS
• Use of 193nm dry lithography
• From 65 nm to 45 nm Tech.
• Tr density: 2 times increase
• Tr switching power: 30% reduction
• Tr switching speed: 20% improvement
• S-D leakage power: 5 times reduction
• Gate oxide leakage: 10 times reduction
• 45nm processors (Core™2 family processors "Penryn")
running Windows* Vista*, Linux* etc.
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Silicon-on-Insulator (SoI)
• Lower parasitic capacitance due to
isolation from the bulk silicon,
• Resistance to latch up due to complete
isolation of the n- and p-well structures.
• Higher performance at equivalentVDD
• Reduced temperature dependency due to no doping.
• Better yield due to high density, better wafer utilization.
• Reduced antenna issues
• No body or well taps are needed.
• Lower leakage currents due to isolation thus higher
power efficiency.
• Inherently radiation hardened ( resistant to soft errors ),
thus reducing the need for redundancy.
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FDSOI
•Fully Depleted
•Very thin layer of
buried oxide
•The region under the
channel is fully
depleted no neutral
region exists.
PDSOI
•Partially Depleted
•Thick layer of
Buried oxide
•Neutral regions
exists under
channel
•Floating body
effect
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Industry use of SoI
• IBM : "Istar" PowerPC-AS microprocessor
• AMD : 130 nm, 90 nm, 65 nm, 45 nm and 32 nm
single, dual, quad, six and eight core processor
• FreeScale: PowerPC 7455 CPU
• Intel did not use SoI in general but moved to HKMG
and Trigate with Conventional CMOS
• As for the traditional foundries, on July 2006, TSMC
claimed no customer wanted SOI
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•More Moore:
•continuous scaling,
•Already up to 7 or 5nm
•Beyond CMOS:
•new technologies such as graphene
•nanowires from the area of
Nanosciences and Nanotechnologies
•More than Moore:
•additional functionalities such as
micro/nanosystem, RF, analog, biochips
on more conventional logic or memory
circuits
76. 11/22/2023 VLSI Technology Trends... 76
Roadmap for Century…..
Courtesy: H. Iwai, Microelectronics. Eng. (2009), doi:10.1016/j.mee.2009.03
77. 11/22/2023 VLSI Technology Trends... 77
Adopt Natural Bio System….
Just for example, brain of the mosquito make the real
time 3D flight control with image processing equipped
with many sensors such as infrared and CO2 with
extremely small brain volume and extremely small
energy consumption. The performance of dragonfly’s
brain is much higher. Today’s performance and energy
consumption of the microprocessor are not comparable
to those of insect brains, at all. Introduction of the
algorithm of the bio system will be the ultimate method
in the roadmap.