In this presentation, all kind of computer Memories are explained. These PPTs are better presentable in Slide Show, that's not possible here, the Explanatory Videos are available at https://www.youtube.com/channel/UCaVNvNzkb01ZMT1GDeITM9w

1. MEMORY
UNIT-6
Mohammad Asif Iqbal
Assistant Professor,
School of CSE,
Deptt of ECE

2. STORAGE ELEMENTS

3. As of now we have studied Registers, and that can typically
store 32/64 bits of information. And if we have a look on the
specification of a PC….
Do u know the size of this video I have uploaded
on YouTube?
Its size is 16MB =16×210KB =16×210×210B =16×210×210×8 BITS
So in this lecture we will try to understand how these things
are related, what is the purpose of these different memory
elements, how these are arrange inside a computer and their
working….

4. Before heading towards the main
content let me show you another
interesting thing
The changes in the size of these memory chips over the period of 5 decayed
The storage space is of 5MB The storage space is of 128GB

5. Dynamic RAM
Static RAM Programmable ROM
Electrically Programmable ROM
Electrically Erasable Programmable ROM
HDD
FDD
DVD
Pen-drive
MEMORY
MEMORY/
PRIMARY
RAM Random
Access Memory
ROM Read Only
Memory
PROM
EPROM
EEPROM
SRAM
DRAM
STORAGE/
SECONDRY
SEMICONDUCTOR MEMORY
Primary memory is the
main memory of the
computer which can be
directly accessed by the
central processing unit,
whereas secondary
memory refers to the
external storage device
which can be used to
store data or information
permanently
Permanent or Semi-
permanent storage of
Data.
These both are random access
& By random access we mean
that all data in any address is
accessible in an equal amount of
time.
TEHN WHAT IS THE
DIFFERENCE B/W ROM & RAM
Read Only. It means You can read only, and most
of its part is permanent, or semi-permanent. i.e. it
cant be written in normal circumstances. It is
NONVOLATILE. Its not going to disappear.
Think about 1 & 0 s engrave into a tiny tiny tiny
stone put in your computer and you cant erase it.
The advantage of ROM is, when you turn it off ,
and you turn it back ON the memory is still there,
So the advantage of ROM is Nonvolatile, but
the disadvantage is you cant write under
normal circumstances
Whereas RAM is Volatile, you turned off
RAM, its gone, but the advantage is you can
Read and Write.

6. SRAM/
DRAM
Select
IN OUT
The block diagram of these Memory Units
Its called a
Cell/Chip

7. Lets see, how these are organized…
MemoryAddress
Register

8. T2T1
Word Line
Bit Lines
SRAM
READ
𝐐 =1 Q=0
BL BL=1 =1
Both BL and BL
are pre-charged to
logic 11 1
But here, you can spot the voltage
difference, that will result in
voltage drop across BL, that will
decrease the value of BL
This is how BL and BL
will be connected with
this sense amplifier
Since there is no voltage
difference, there wont be
any change in the value
of BL or 𝐐
0
Now here comes your sense
amplifier. Do u remember this??
Its a simple comparator. And its
output will be high (logic 1) only if
V+ > V_.
As we have previously discussed that BL >> BL,
it implies that V+ < V_. so we can anticipate the
output of the sense amplifier, and that will be 0,
hence we have read the content of this RAM.

9. T2T1
Word Line
Bit Lines
SRAM
WRITE
1 0
𝐐 =0 Q=1
BL BL

10. Word Line
Bit Lines
Example of a CMOS Memory Cell
T2T1
Vsupply
Ground
𝐐 Q
BL BL

11. 0ON
S
D
G
PMOS
1
S
D
G
CMOS INVERTER

12. Q=𝐐 =
Example of a CMOS Memory Cell
1 0
1
ON
1 OFF
0
OFF
0ON
Word Line
Vsupply
Ground
Bit Lines
T2T1
T3 T4
T6T5
BL BL

13. Word Line
Bit Lines
Example of a CMOS Memory Cell
T2T1
Vsupply
Ground
𝐐 Q
BL BL
T3 T4
T6T5
That’s why it is known as 6T SRAM
Cant we design this
with less number of
Transistor?
We can!! Lets see,
How?

14. Word Line
Bit Lines
T2T1
Vsupply
Ground
𝐐 Q
BL BL
T3 T4
T6T5
Lets try designing it
with the help of NMOS
only, so we have to
remove the PMOS, lets
do that.
R1 R2
This is known as 4T SRAM This circuit is also having the same
function, and will perfectly work as a
SRAM. Even with less number of
Transistor, and hence with comparatively
less space requirement. Then the
question is why we have studied 6T-SRAM
Now we will replace these transistor
with Resistor, that wont change the
operation of circuit and it will still
work as an inverter
The reason is, 6T SRAM is having less
Power Dissipation(PD), because of
CMOS, and this 4T SRAM has
comparatively greater PD, because of
the presence of Resisters.
In conclusion we can say, that we may use
both of them, depending on the
requirement. If in certain system we are
more concern about space, then Power
Dissipation, we will surely go for 4T, and
vice-versa

15. DRAMS
1
S
D
G

16. DRAMS
Word Line
Bit Line
BL
This capacitor will store the information
in the form of Electric Charge.
WRITE =1 Now there is no connection between BL
and capacitor, so the charge will be stored
in the capacitor, and will be considered as
logic 1. That’s how 1 is written in DRAM.
But, the charge stored in capacitor will
gradually leak out, so in order to retain
the content of DRAM we have to
periodically refresh them, that’s drives
its name as Dynamic RAM.
Apart from this disadvantage, the main
advantage of DRAM is its comparatively
small size, that makes it less expensive.
Similarly if BL is at logic zero, then the
capacitor wont get charged, and it will
also consider to be at logic zero. That's
how 0 is written in DRAM

17. Word Line
Bit Line
READ Bit Line
10
In actual practice, there are Millions and
Billions of these kind of DRAMs are arranged in
this way. In this arrangement as you can see, we
have divided this entire mesh by an array of
sense amplifiers. Now lets again focus on these
two DRAMS only.
Having understood the arrangement of bit
Lines, now we can extend this Bit Lines little
further considering they are connected with
other DRAMs, placed at different memory
location. Sense Amplifier Sense Amplifier
These Bit Lines are pre-charged, to the half
of the value of system voltage. Lets say they are
at 2.5V
2.5V 2.5V
2.5V 2.5V
Now if the capacitor is charged up, the charge
will move from the capacitor to bit line. That
will increase the potential at Bit Line a little bit.
Lets say by an amount of δ.
+ δ
This small difference between the values of Bit
Lines will be sensed by the Sense Amplifier, and
it will produce an output based on following
logic; if V+ > V_ output will be 1
And if V+ < V_ output will be 0
= 1
Now, in this case, the capacitor is not charged,
so charge will move from the bit line to the
capacitor, that will decrease the value of Bit
Line a little bit, let say by an amount of δ.
̶ δ
= 0
In last one important thing to observe is this
Read operation is destructive. i.e. the total
charged in both the cases has changed. This will
be cope up by that periodic refreshing process
explained earlier.

18. ROM
A read‐only memory (ROM) is essentially a memory device in which permanent binary
information is stored. The binary information must be specified by the designer and is then
embedded in the unit to form the required interconnection pattern. Once the pattern is
established, it stays within the unit even when power is turned off and on again.

19. k×2k
Decoder
.
.
.
k
Inputs
.
.
.
.
2k
Outputs
of
decoder
.
.
.
.
n outputs
2k×n
A block diagram of a ROM consisting of k
inputs and n outputs is shown in the inputs
provide the address for memory, and the
outputs give the data bits of the stored word
that is selected by the address.
A block diagram of a ROM consisting of k
inputs &n outputs
where the inputs provide the address for
memory, and the outputs give the data bits
of the stored word that is selected by the
address.

20. 3×8
A
B
C
A’B’C’
A’B’C
A’BC’
A’BC
AB’C’
AB’C
ABC’
ABC
U V W X Y Z
The internal binary storage of a ROM is
specified by a truth table that shows
the word content in each address. For
example, the content of a 8×6 ROM may
be specified with a truth table similar
to the one shown in following table
=0
=0
=0
1 0 1 0 0 1Now, according to the required Data
set what we have to store in the ROM,
we will make changes in the ROM. A
connection that we have made by a
cross, will represent 1 and absence of
connection represents 0.
=0
=0
=1
0 1 0 1 1 1

21. INPUTS
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
OUTPUTS
U V W X Y Z
1 0 1 0 0 1
0 1 0 1 1 1
1 1 0 0 0 1
0 0 1 0 0 0
0 0 1 1 1 1
0 1 0 1 0 1
1 1 0 1 1 1
1 0 1 1 1 1
Combinational Circuit Implementation using ROM
Lets say we have got a combinational
circuit define by the following truth
table.

22. 3×8
A
B
C
U
1
0
1
0
0
0
1
1
A’B’C’
A’B’C
A’BC’
A’BC
AB’C’
AB’C
ABC’
ABC
U V W X Y Z
O/P
Minterms
0 A’B’C’
1 A’B’C
2 A’BC’
3 AB’C’
4 A’BC
5 A’BC’
6 ABC’
7 ABC
V
0
1
1
0
0
1
1
0
OUTPUTS
W X Y Z
1 0 0 1
0 1 1 1
0 0 0 1
1 0 0 0
1 1 1 1
0 1 0 1
0 1 1 1
1 1 1 1

23. The procedure for fabricating a ROM requires that the customer fill out the truth table he or
she wishes the ROM to satisfy. The manufacturer makes the corresponding mask for the
paths to produce the 1’s and 0’s according to the customer’s truth table. This procedure is
costly because the vendor charges the customer a special fee for custom masking the
particular ROM
PROM
For small quantities, it is more economical to use a second type of ROM called
Programmable Read‐Only Memory, or PROM. When ordered, PROM
units contain all the fuses intact, giving all 1’s in the bits of the stored words. The fuses in the
PROM are blown by the application of a high‐voltage pulse to the device through a special
pin. A blown fuse defines a binary 0 state and an intact fuse gives a binary 1 state. This
procedure allows the user to program the PROM in the laboratory to achieve the desired
relationship between input addresses and stored words. Special instruments called PROM
programmers are available commercially to facilitate the procedure.

24. 3×8
A
B
C
A’B’C’
A’B’C
A’BC’
A’BC
AB’C’
AB’C
ABC’
ABC
U V W X Y ZU= A’B’C +A’BC’ +AB’C’ +AB’C +ABC
U= A’B’C’+A’B’C +A’BC’ +A’BC +AB’C’
+AB’C +ABC’ +ABC
When all the fuse are intact,
output U will be the sum of
all Minterms
Lets say, for any particular
function, we ant U to be
equals to this…
The easiest way to realize
this function is to remove
the minterms what we
don’t need, and that can be
simply achieve by blowing
the related fuses, by
following the methods
discussed earlier.
Fix AND
Array
Programmable OR
Array

25. EPROM:-Erasable, reprogrammable ROM
They may store information for long time but not for infinite time some
says for 100 years So they may be used in place of ROM.
In this we use a special type of transistor known as FGMOS (Floating-
Gate MOSFET)
The special characteristic of this transistor is that it may be used as a
normal transistor or as a disabled transistor that is always turned off.
The important advantage of EPROM chip is that their content can be
erased and reprogrammed
For erasing we have to erase the charges trapped in the transistor of
the memory cell; which is achieved by exposing it to the Ultraviolet
light. This is the reason of this transparent window.

26. EEPROM
A significant disadvantage of EPROMS is that a chip must be physically
removed from the circuit for reprogramming and that its entire
contents are erased by the ultraviolet light.
So an other ROM came into existence that can be both programmed
and erased electrically. Such chips are called EEPROM (Electrically
erasable PROM)
Moreover it is possible to erase the cell content selectively.
The only disadvantage of EEPROM is that different voltages are needed
for erasing, writing and reading the stored data.

27. Combinational PLDs
The PROM is a
combinational
programmable logic
device (PLD)—an
integrated circuit with
programmable gates
divided into an AND
array and an OR array to
provide an AND–OR
sum‐of‐product
implementation. There
are three major types of
combinational PLDs,
differing in the
placement of the
programmable
connections in the AND–
OR array.
Programmable
AND Array
Fixed OR Array
Fix AND Array
(Decoder)
Programmable OR
Array
Programmable
AND Array
Programmable OR
Array
Inputs outputs
Inputs outputs
Inputs outputs
Programmable read-only memory (PROM)
Programmable array logic (PAL)
Programmable logic array (PLA)

28. PLA
The PLA is similar in concept to the PROM, except that the PLA does not provide
full decoding of the variables and does not generate all the minterms. The decoder
is replaced by an array of AND gates that can be programmed to generate any
product term of the input variables. The product terms are then connected to OR
gates to provide the sum of products for the required Boolean functions.

29. A B C
A B CA’ B’ C’
These Buffer-Inverter combinations
will provide both true and
complemented outputs
Each input and its complement are
connected to the inputs of each
AND gate, with the help of these we
can generate any product term
The outputs of the AND
gates are connected to the inputs of
each OR gate
The output of the OR gate goes to an
XOR gate, where the other input can be
programmed to receive a signal equal to
either logic 1 or logic 0. The output is
inverted when the XOR input is
connected to 1 (since x ⊕ 1 = x’ ). The
output does not change when the XOR
input is connected to 0 (since x ⊕ 0 = x)
0
1

30. Implementation using PLA
F1 = AB’ + AC + A’BC’
F2 = (AC + BC)’
Lets say, we want to implement this
function using PLA
First we have to define the size of PLA
That can be done by considering the following
Number of inputs variables = Total number of Buffer-inverter
Total number of distinct product terms= Number of AND gate
Total number of Outputs(functions)= Number of OR gates.
So in this case
Number of inputs variables = Total number of Buffer-inverter = 3
Total number of distinct product terms= Number of AND gate = 4
Total number of Outputs(functions)= Number of OR gates = 2

31. PLA Programming Table
Following Programming table may also be drawn for these functions
F1 = AB’ + AC + A’BC’
F2 = (AC + BC)’
Outputs
Inputs (T) (C)
Product
Terms
A B C F1 F2
AB’ 1 1 0 — 1 —
AC 2 1 — 1 1 1
BC 3 0 1 1 — 1
A’BC’ 4 0 1 0 1 —
T (true) output dictates that the other
input of the corresponding XOR gate be
connected to 0, and a C (complement)
specifies a connection to 1

32. A B C
A B CA’ B’ C’
0
1
×
Now, we will see the implementation
×
× ×
× ×
× × ×
×AB’
AC
BC
A’BC’
×
× ×
×
×
×
F1
F2

33. Programmable Array Logic (PAL)
The PAL is a programmable logic device with a fixed OR array and a programmable
AND array. Because only the AND gates are programmable, the PAL is easier to
program than, but is not as flexible as, the PLA.

34. A B C
A B CA’ B’ C’
Now lets say we have to realize this function
F1 = AB’ + AC + A’BC’
F2 = AC + BC
× ×
× ×
× ××
AB’
AC
A’BC’
F1
× ×
× ×
AC
BC
×
×
F2
Each input has a buffer–
inverter gate, and each
output is generated by a
fixed OR gate.
There are three sections in
the unit, each composed of
an AND–OR array that is
three wide, the term used to
indicate that there are three
programmable AND gates
in each section and one
fixed OR gate
Implementation using PAL

35. THANK YOU!